24 lines
266 B
Verilog
24 lines
266 B
Verilog
module seqBlinkTB();
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reg clock;
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wire [3:0] leds;
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seqBlink uut(clock, leds);
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initial begin
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clock = 0;
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forever begin
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#5 clock = ~clock;
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end
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end
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initial begin
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$dumpfile("lab5v.vcd");
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$dumpvars;
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#100;
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$finish;
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end
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endmodule |