2024-12-02 02:29:57 +03:00

14 lines
226 B
Verilog

module orGate (
input A_i,
input B_i,
output F_o
);
wire nand1_out, nand2_out;
nand nand1 (nand1_out, A_i, A_i);
nand nand2 (nand2_out, B_i, B_i);
nand nand3 (F_o, nand1_out, nand2_out);
endmodule