$date
	Thu Jan 30 07:38:04 2025
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module bib3AdvancedTB $end
$var wire 4 ! sonuc [3:0] $end
$var wire 1 " bitti $end
$var reg 1 # basla $end
$var reg 9 $ buyruk [8:0] $end
$var reg 1 % clk $end
$var integer 32 & i [31:0] $end
$scope module uut $end
$var wire 1 # basla $end
$var wire 9 ' buyruk [8:0] $end
$var wire 1 % clk $end
$var reg 1 " bitti $end
$var reg 4 ( sonuc [3:0] $end
$var integer 32 ) a [31:0] $end
$var integer 32 * b [31:0] $end
$var integer 32 + c [31:0] $end
$var integer 32 , count [31:0] $end
$var integer 32 - i [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
bx -
bx ,
bx +
bx *
bx )
bx (
b0 '
bx &
0%
b0 $
0#
x"
bx !
$end
#5
b0 !
b0 (
0"
1%
#10
0%
b1001 $
b1001 '
b0 &
1#
#15
1"
b10 !
b10 (
1%
#20
0%
b1100001 $
b1100001 '
b1 &
#25
b11 !
b11 (
1"
1%
#30
0%
b10100101 $
b10100101 '
b10 &
#35
b100 !
b100 (
1"
1%
#40
0%
b11100011 $
b11100011 '
b11 &
#45
b111 !
b111 (
1"
1%
#50
0%
b100111111 $
b100111111 '
b100 &
#55
b1111 !
b1111 (
1"
b101 -
1%
#60
0%
b100100001 $
b100100001 '
b101 &
#65
b0 !
b0 (
1"
b101 -
1%
#70
0%
b101100001 $
b101100001 '
b110 &
#75
b1111 !
b1111 (
1"
b110 )
1%
#80
0%
b110100001 $
b110100001 '
b111 &
#85
1"
b110 *
b10 ,
1%
#90
0%
b111100001 $
b111100001 '
b1000 &
#95
b0 !
b0 (
1"
b110 +
b10 ,
1%
#100
0%
b1001 $
b1001 '
b1001 &
#105
b10 !
b10 (
1"
1%
#110
0%
b1100001 $
b1100001 '
b1010 &
#115
b11 !
b11 (
1"
1%
#120
0%
b10100101 $
b10100101 '
b1011 &
#125
b100 !
b100 (
1"
1%
#130
0%
b11100011 $
b11100011 '
b1100 &
#135
b111 !
b111 (
1"
1%
#140
0%
b100111111 $
b100111111 '
b1101 &
#145
b1111 !
b1111 (
1"
b101 -
1%
#150
0%
b100100001 $
b100100001 '
b1110 &
#155
b0 !
b0 (
1"
b101 -
1%
#160
0%
b101100001 $
b101100001 '
b1111 &
#165
b1111 !
b1111 (
1"
b110 )
1%
#170
0%
bx $
bx '
b10000 &
#175
b0 !
b0 (
0"
1%
#180
0%
0#
b10001 &
#185
1%
#190
0%