25 lines
355 B
Verilog
25 lines
355 B
Verilog
module subtractionTB();
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reg [3:0] A, B;
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wire [4:0] Y;
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wire overflow;
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subtraction uut (
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.A(A),
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.B(B),
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.Y(Y)
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);
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assign overflow = uut.overflow;
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initial begin
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$dumpfile("subtraction.vcd");
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$dumpvars;
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A = 4'b0101; B = 4'b0100; #5;
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A = 4'b1000; B = 4'b0111; #5;
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A = 4'b0101; B = 4'b1000; #5;
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$finish;
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end
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endmodule
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