28 lines
636 B
Verilog
28 lines
636 B
Verilog
module subtraction (
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input [3:0] A, B,
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input CarryIN,
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output [3:0] Y,
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output CarryOUT,
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output overflow
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);
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wire [3:0] xB;
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wire [3:0] notB;
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wire [3:0] Y1;
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not n1 (xB[0], B[0]);
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not n2 (xB[1], B[1]);
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not n3 (xB[2], B[2]);
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not n4 (xB[3], B[3]);
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addition a1 (.A(xB), .B(4'b0001), .CarryIN(1'b0), .Y(notB));
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addition a2 (.A(A), .B(notB[3:0]), .CarryIN(CarryIN), .Y(Y1), .CarryOUT(CarryOUT));
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overflowDetect od1 (.opCode(2'b10), .A(A), .B(B), .Y(Y1), .CarryOUT(CarryOUT), .overflowDetect(overflow));
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or o1 (Y[0], Y1[0], 1'b0);
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or o2 (Y[1], Y1[1], 1'b0);
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or o3 (Y[2], Y1[2], 1'b0);
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or o4 (Y[3], Y1[3], 1'b0);
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endmodule
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