151 lines
1.4 KiB
Plaintext
151 lines
1.4 KiB
Plaintext
$date
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Sat Dec 14 03:32:40 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module logicUnitTB $end
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$var wire 4 ! resultX [3:0] $end
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$var wire 4 " resultO [3:0] $end
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$var wire 4 # resultA [3:0] $end
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$var reg 4 $ A [3:0] $end
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$var reg 4 % B [3:0] $end
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$var reg 3 & opCode [2:0] $end
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$scope module uut $end
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$var wire 4 ' A [3:0] $end
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$var wire 4 ( B [3:0] $end
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$var wire 3 ) opCode [2:0] $end
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$var wire 4 * xor1 [3:0] $end
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$var wire 4 + resultX [3:0] $end
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$var wire 4 , resultO [3:0] $end
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$var wire 4 - resultA [3:0] $end
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$var wire 4 . or1 [3:0] $end
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$var wire 4 / and1 [3:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b1 /
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b1 .
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b1 -
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b0 ,
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b0 +
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b0 *
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b1 )
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b1 (
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b1 '
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b1 &
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b1 %
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b1 $
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b1 #
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b0 "
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b0 !
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$end
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#2
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b11 .
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b10 *
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b11 $
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b11 '
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#4
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b1001 #
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b1001 -
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b1001 /
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b1001 .
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b0 *
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b1001 %
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b1001 (
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b1001 $
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b1001 '
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#6
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b1111 #
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b1111 -
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b1111 /
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b1111 .
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b1111 %
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b1111 (
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b1111 $
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b1111 '
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#8
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b0 #
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b0 -
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b0 /
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b0 .
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b0 %
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b0 (
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b0 $
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b0 '
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#10
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b101 "
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b101 ,
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b100 *
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b1 /
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b101 .
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b101 %
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b101 (
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b1 $
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b1 '
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b10 &
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b10 )
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#12
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b1101 "
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b1101 ,
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b1101 .
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b1100 *
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b1001 $
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b1001 '
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#14
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b1111 "
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b1111 ,
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b1111 .
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b1110 *
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b1111 %
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b1111 (
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b1 $
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b1 '
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#16
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b101 "
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b101 ,
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b101 .
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b0 /
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b101 *
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b101 %
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b101 (
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b0 $
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b0 '
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#18
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b0 "
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b0 ,
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b101 !
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b101 +
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b100 &
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b100 )
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#20
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b0 !
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b0 +
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b0 .
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b0 *
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b0 %
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b0 (
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#22
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b101 !
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b101 +
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b101 .
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b101 *
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b101 %
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b101 (
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#24
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b0 !
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b0 +
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b1111 /
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b1111 .
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b0 *
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b1111 %
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b1111 (
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b1111 $
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b1111 '
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#26
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