29 lines
615 B
Verilog
29 lines
615 B
Verilog
module fulladderTB();
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reg A, B, CarryIn;
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wire Sum, CarryOut;
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fulladder uut(
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.A(A),
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.B(B),
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.CarryIn(CarryIn),
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.Sum(Sum),
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.CarryOut(CarryOut)
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);
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initial begin
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$dumpfile("fulladder.vcd");
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$dumpvars;
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A = 1'b0; B = 1'b0; CarryIn = 1'b0; #10;
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A = 1'b0; B = 1'b0; CarryIn = 1'b1; #10;
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A = 1'b0; B = 1'b1; CarryIn = 1'b0; #10;
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A = 1'b0; B = 1'b1; CarryIn = 1'b1; #10;
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A = 1'b1; B = 1'b0; CarryIn = 1'b0; #10;
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A = 1'b1; B = 1'b0; CarryIn = 1'b1; #10;
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A = 1'b1; B = 1'b1; CarryIn = 1'b0; #10;
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A = 1'b1; B = 1'b1; CarryIn = 1'b1; #10;
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$finish;
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end
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endmodule
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