85 lines
915 B
Plaintext
85 lines
915 B
Plaintext
$date
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Thu Dec 12 00:41:38 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module fulladderTB $end
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$var wire 1 ! Sum $end
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$var wire 1 " CarryOut $end
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$var reg 1 # A $end
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$var reg 1 $ B $end
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$var reg 1 % CarryIn $end
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$scope module uut $end
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$var wire 1 # A $end
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$var wire 1 $ B $end
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$var wire 1 % CarryIn $end
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$var wire 1 " CarryOut $end
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$var wire 1 ! Sum $end
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$var wire 1 & AxorB $end
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$var wire 1 ' AandB $end
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$var wire 1 ( ABandCIn $end
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$scope module h1 $end
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$var wire 1 # A $end
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$var wire 1 $ B $end
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$var wire 1 ' CarryOut $end
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$var wire 1 & Sum $end
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$upscope $end
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$scope module h2 $end
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$var wire 1 & A $end
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$var wire 1 % B $end
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$var wire 1 ( CarryOut $end
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$var wire 1 ! Sum $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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0(
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0'
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0&
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0%
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0$
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0#
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0"
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0!
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$end
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#10
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1!
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1%
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#20
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1&
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0%
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1$
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#30
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1"
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0!
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1(
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1%
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#40
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0"
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1!
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0(
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0%
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0$
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1#
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#50
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1"
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0!
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1(
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1%
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#60
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0(
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0&
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1'
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0%
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1$
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#70
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1!
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1%
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#80
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