30 lines
541 B
Verilog
30 lines
541 B
Verilog
module bit3AdderTB();
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reg [2:0] A;
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reg [2:0] B;
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wire [3:0] Sum;
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bit3Adder uut (
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.A(A),
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.B(B),
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.Sum(Sum)
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);
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initial begin
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$dumpfile("bit3Adder.vcd");
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$dumpvars;
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A = 3'b000; B = 3'b000; #10;
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A = 3'b000; B = 3'b001; #10;
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A = 3'b001; B = 3'b001; #10;
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A = 3'b010; B = 3'b010; #10;
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A = 3'b010; B = 3'b011; #10;
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A = 3'b110; B = 3'b010; #10;
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A = 3'b101; B = 3'b100; #10;
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A = 3'b111; B = 3'b100; #10;
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A = 3'b111; B = 3'b110; #10;
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A = 3'b111; B = 3'b111; #10;
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$finish;
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end
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endmodule
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