213 lines
2.1 KiB
Plaintext
213 lines
2.1 KiB
Plaintext
$date
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Thu Dec 12 01:03:03 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module bit3AdderTB $end
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$var wire 4 ! Sum [3:0] $end
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$var reg 3 " A [2:0] $end
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$var reg 3 # B [2:0] $end
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$scope module uut $end
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$var wire 3 $ A [2:0] $end
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$var wire 3 % B [2:0] $end
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$var wire 4 & Sum [3:0] $end
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$var wire 3 ' Carry3 [2:0] $end
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$scope module f1 $end
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$var wire 1 ( A $end
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$var wire 1 ) B $end
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$var wire 1 * CarryIn $end
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$var wire 1 + CarryOut $end
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$var wire 1 , Sum $end
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$var wire 1 - AxorB $end
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$var wire 1 . AandB $end
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$var wire 1 / ABandCIn $end
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$scope module h1 $end
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$var wire 1 ( A $end
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$var wire 1 ) B $end
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$var wire 1 . CarryOut $end
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$var wire 1 - Sum $end
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$upscope $end
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$scope module h2 $end
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$var wire 1 - A $end
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$var wire 1 * B $end
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$var wire 1 / CarryOut $end
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$var wire 1 , Sum $end
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$upscope $end
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$upscope $end
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$scope module f2 $end
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$var wire 1 0 A $end
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$var wire 1 1 B $end
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$var wire 1 2 CarryIn $end
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$var wire 1 3 CarryOut $end
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$var wire 1 4 Sum $end
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$var wire 1 5 AxorB $end
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$var wire 1 6 AandB $end
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$var wire 1 7 ABandCIn $end
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$scope module h1 $end
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$var wire 1 0 A $end
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$var wire 1 1 B $end
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$var wire 1 6 CarryOut $end
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$var wire 1 5 Sum $end
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$upscope $end
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$scope module h2 $end
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$var wire 1 5 A $end
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$var wire 1 2 B $end
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$var wire 1 7 CarryOut $end
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$var wire 1 4 Sum $end
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$upscope $end
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$upscope $end
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$scope module h1 $end
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$var wire 1 8 A $end
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$var wire 1 9 B $end
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$var wire 1 : CarryOut $end
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$var wire 1 ; Sum $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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0;
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0:
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09
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08
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07
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06
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05
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04
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03
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02
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01
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00
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0/
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0.
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0-
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0,
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0+
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0*
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0)
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0(
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bz00 '
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b0 &
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b0 %
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b0 $
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b0 #
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b0 "
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b0 !
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$end
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#10
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b1 !
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b1 &
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1;
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19
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b1 #
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b1 %
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#20
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1,
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1*
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b10 !
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b10 &
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0;
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bz01 '
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1:
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18
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b1 "
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b1 $
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#30
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14
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b100 !
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b100 &
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0,
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12
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0*
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1+
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bz10 '
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0:
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1.
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09
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1)
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08
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1(
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b10 #
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b10 %
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b10 "
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b10 $
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#40
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b101 !
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b101 &
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1;
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19
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b11 #
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b11 %
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#50
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13
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04
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17
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b1000 !
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b1000 &
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0;
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15
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09
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10
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b10 #
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b10 %
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b110 "
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b110 $
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#60
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02
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04
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07
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bz00 '
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0+
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05
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16
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b1001 !
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b1001 &
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1;
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0.
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0)
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11
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18
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0(
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b100 #
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b100 %
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b101 "
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b101 $
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#70
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b1011 !
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b1011 &
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1,
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1-
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1(
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b111 "
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b111 $
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#80
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14
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12
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b1101 !
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b1101 &
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0,
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bz10 '
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1+
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0-
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1.
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1)
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b110 #
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b110 %
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#90
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1,
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1*
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b1110 !
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b1110 &
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0;
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bz11 '
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1:
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19
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b111 #
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b111 %
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#100
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