14 lines
362 B
Verilog
14 lines
362 B
Verilog
module bit3Adder (
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input [2:0] A,
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input [2:0] B,
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output [3:0] Sum
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);
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wire [2:0] Carry3;
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halfadder h1(.A(A[0]), .B(B[0]), .Sum(Sum[0]), .CarryOut(Carry3[0]));
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fulladder f1(.A(A[1]), .B(B[1]), .CarryIn(Carry3[0]), .Sum(Sum[1]), .CarryOut(Carry3[1]));
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fulladder f2(.A(A[2]), .B(B[2]), .CarryIn(Carry3[1]), .Sum(Sum[2]), .CarryOut(Sum[3]));
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endmodule
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