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kaltinsoy/verilog

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kaltinsoy committed 2024-12-02 02:42:36 +03:00

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commit f0551ce34f

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										iverilog/nand2tetris/nands/notGate.v
									
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				@@ -1,5 +1,7 @@

				module notGate (input A,

				                output B);

				module notGate (

				    input  A,

				    output B

				);

				   nand nand1 (B, A, A);

				endmodule