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formatter test

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k0rrluna
2024-12-02 02:42:36 +03:00
parent 1cb96c9f9a
commit f0551ce34f
3 changed files with 45 additions and 43 deletions
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6
iverilog/nand2tetris/nands/notGate.v
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@ -1,5 +1,7 @@
module notGate (input A, module notGate (
output B); input A,
output B
);
nand nand1 (B, A, A); nand nand1 (B, A, A);
endmodule endmodule