verilog
This commit is contained in:
24
lab2/impl/gwsynthesis/lab2.log
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24
lab2/impl/gwsynthesis/lab2.log
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GowinSynthesis start
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Running parser ...
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Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\BitM.v'
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Compiling module 'BitM'("C:\cygwin64\home\koray\verilog\lab2\src\BitM.v":1)
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NOTE (EX0101) : Current top module is "BitM"
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[5%] Running netlist conversion ...
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Running device independent optimization ...
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[10%] Optimizing Phase 0 completed
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[15%] Optimizing Phase 1 completed
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[25%] Optimizing Phase 2 completed
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Running inference ...
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[30%] Inferring Phase 0 completed
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[40%] Inferring Phase 1 completed
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[50%] Inferring Phase 2 completed
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[55%] Inferring Phase 3 completed
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Running technical mapping ...
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[60%] Tech-Mapping Phase 0 completed
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[65%] Tech-Mapping Phase 1 completed
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[75%] Tech-Mapping Phase 2 completed
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[80%] Tech-Mapping Phase 3 completed
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[90%] Tech-Mapping Phase 4 completed
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[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg" completed
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[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2_syn.rpt.html" completed
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GowinSynthesis finish
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19
lab2/impl/gwsynthesis/lab2.prj
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19
lab2/impl/gwsynthesis/lab2.prj
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE gowin-synthesis-project>
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<Project>
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<Version>beta</Version>
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<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
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<FileList>
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<File path="C:\cygwin64\home\koray\verilog\lab2\src\BitM.v" type="verilog"/>
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</FileList>
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<OptionList>
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<Option type="disable_insert_pad" value="0"/>
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<Option type="global_freq" value="100.000"/>
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<Option type="looplimit" value="2000"/>
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<Option type="output_file" value="C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg"/>
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<Option type="print_all_synthesis_warning" value="0"/>
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<Option type="ram_rw_check" value="0"/>
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<Option type="verilog_language" value="verilog-2001"/>
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<Option type="vhdl_language" value="vhdl-1993"/>
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</OptionList>
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</Project>
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76
lab2/impl/gwsynthesis/lab2.vg
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76
lab2/impl/gwsynthesis/lab2.vg
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//
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//Written by GowinSynthesis
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//Tool Version "V1.9.9.02"
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//Thu Apr 11 07:46:56 2024
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//Source file index table:
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//file0 "\C:/cygwin64/home/koray/verilog/lab2/src/BitM.v"
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`timescale 100 ps/100 ps
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module BitM (
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A,
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B,
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AlB,
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AeB,
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AgB
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)
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;
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input A;
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input B;
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output AlB;
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output AeB;
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output AgB;
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wire A_d;
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wire B_d;
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wire AlB_d;
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wire AgB_d;
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wire AeB_d;
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wire VCC;
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wire GND;
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IBUF A_ibuf (
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.O(A_d),
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.I(A)
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);
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IBUF B_ibuf (
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.O(B_d),
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.I(B)
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);
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OBUF AlB_obuf (
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.O(AlB),
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.I(AlB_d)
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);
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OBUF AeB_obuf (
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.O(AeB),
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.I(AeB_d)
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);
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OBUF AgB_obuf (
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.O(AgB),
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.I(AgB_d)
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);
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LUT2 AlB_d_s (
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.F(AlB_d),
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.I0(A_d),
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.I1(B_d)
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);
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defparam AlB_d_s.INIT=4'h4;
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LUT2 AgB_d_s (
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.F(AgB_d),
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.I0(B_d),
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.I1(A_d)
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);
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defparam AgB_d_s.INIT=4'h4;
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LUT2 AeB_d_s (
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.F(AeB_d),
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.I0(A_d),
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.I1(B_d)
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);
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defparam AeB_d_s.INIT=4'h9;
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VCC VCC_cZ (
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.V(VCC)
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);
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GND GND_cZ (
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.G(GND)
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);
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GSR GSR (
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.GSRI(VCC)
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);
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endmodule /* BitM */
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167
lab2/impl/gwsynthesis/lab2_syn.rpt.html
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167
lab2/impl/gwsynthesis/lab2_syn.rpt.html
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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<html>
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<head>
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<title>synthesis Report</title>
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<style type="text/css">
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body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
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div#main_wrapper{ width: 100%; }
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div#content { margin-left: 350px; margin-right: 30px; }
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div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
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div#catalog ul { list-style-type: none; }
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div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
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div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
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div#catalog a:visited { color: #0084ff; }
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div#catalog a:hover { color: #fff; background: #0084ff; }
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hr { margin-top: 30px; margin-bottom: 30px; }
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h1, h3 { text-align: center; }
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h1 {margin-top: 50px; }
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table, th, td { border: 1px solid #aaa; }
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table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
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th, td { padding: 5px 5px 5px 5px; }
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th { color: #fff; font-weight: bold; background-color: #0084ff; }
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table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
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table.detail_table td.label { min-width: 100px; width: 8%;}
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</style>
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</head>
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<body>
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<div id="main_wrapper">
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<div id="catalog_wrapper">
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<div id="catalog">
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<ul>
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<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
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<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
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<li><a href="#resource" style=" font-size: 16px;">Resource</a>
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<ul>
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<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
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<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
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</ul>
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</li>
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</ul>
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</div><!-- catalog -->
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</div><!-- catalog_wrapper -->
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<div id="content">
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<h1><a name="about">Synthesis Messages</a></h1>
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<table class="summary_table">
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<tr>
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<td class="label">Report Title</td>
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<td>GowinSynthesis Report</td>
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</tr>
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<tr>
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<td class="label">Design File</td>
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<td>C:\cygwin64\home\koray\verilog\lab2\src\BitM.v<br>
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</td>
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</tr>
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<tr>
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<td class="label">GowinSynthesis Constraints File</td>
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<td>---</td>
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</tr>
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<tr>
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<td class="label">Tool Version</td>
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<td>V1.9.9.02</td>
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</tr>
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<tr>
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<td class="label">Part Number</td>
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<td>GW2A-LV18PG256C8/I7</td>
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</tr>
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<tr>
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<td class="label">Device</td>
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<td>GW2A-18</td>
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</tr>
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<tr>
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<td class="label">Device Version</td>
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<td>C</td>
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</tr>
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<tr>
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<td class="label">Created Time</td>
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<td>Thu Apr 11 07:46:56 2024
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</td>
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</tr>
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<tr>
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<td class="label">Legal Announcement</td>
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<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
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</tr>
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</table>
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<h1><a name="summary">Synthesis Details</a></h1>
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<table class="summary_table">
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<tr>
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<td class="label">Top Level Module</td>
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<td>BitM</td>
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</tr>
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<tr>
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<td class="label">Synthesis Process</td>
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<td>Running parser:<br/> CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 181.887MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.132s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>Generate output files:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 181.887MB<br/></td>
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</tr>
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<tr>
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<td class="label">Total Time and Memory Usage</td>
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<td>CPU time = 0h 0m 0.108s, Elapsed time = 0h 0m 0.221s, Peak memory usage = 181.887MB</td>
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</tr>
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</table>
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<h1><a name="resource">Resource</a></h1>
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<h2><a name="usage">Resource Usage Summary</a></h2>
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<table class="summary_table">
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<tr>
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<td class="label"><b>Resource</b></td>
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<td><b>Usage</b></td>
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</tr>
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<tr>
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<td class="label"><b>I/O Port </b></td>
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<td>5</td>
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</tr>
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<tr>
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<td class="label"><b>I/O Buf </b></td>
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<td>5</td>
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</tr>
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<tr>
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<td class="label">    IBUF</td>
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<td>2</td>
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</tr>
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<tr>
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<td class="label">    OBUF</td>
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<td>3</td>
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</tr>
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<tr>
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<td class="label"><b>LUT </b></td>
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<td>3</td>
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</tr>
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<tr>
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<td class="label">    LUT2</td>
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<td>3</td>
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</tr>
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</table>
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<h2><a name="utilization">Resource Utilization Summary</a></h2>
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<table class="summary_table">
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<tr>
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<td class="label"><b>Resource</b></td>
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<td><b>Usage</b></td>
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<td><b>Utilization</b></td>
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</tr>
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<tr>
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<td class="label">Logic</td>
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<td>3(3 LUT, 0 ALU) / 20736</td>
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<td><1%</td>
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</tr>
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<tr>
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<td class="label">Register</td>
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<td>0 / 16173</td>
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<td>0%</td>
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</tr>
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<tr>
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<td class="label">  --Register as Latch</td>
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<td>0 / 16173</td>
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<td>0%</td>
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</tr>
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<tr>
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<td class="label">  --Register as FF</td>
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<td>0 / 16173</td>
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<td>0%</td>
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</tr>
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<tr>
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<td class="label">BSRAM</td>
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<td>0 / 46</td>
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<td>0%</td>
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</tr>
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</table>
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</div><!-- content -->
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</div><!-- main_wrapper -->
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</body>
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</html>
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46
lab2/impl/gwsynthesis/lab2_syn_resource.html
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46
lab2/impl/gwsynthesis/lab2_syn_resource.html
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@ -0,0 +1,46 @@
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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<html>
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<head>
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<title>Hierarchy Module Resource</title>
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<style type="text/css">
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body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
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div#main_wrapper{ width: 100%; }
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h1 {text-align: center; }
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h1 {margin-top: 36px; }
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table, th, td { border: 1px solid #aaa; }
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table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
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th, td { align = "center"; padding: 5px 2px 5px 5px; }
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th { color: #fff; font-weight: bold; background-color: #0084ff; }
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table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
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</style>
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</head>
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<body>
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<div id="main_wrapper">
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<div id="content">
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<h1>Hierarchy Module Resource</h1>
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<table>
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<tr>
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<th class="label">MODULE NAME</th>
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<th class="label">REG NUMBER</th>
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<th class="label">ALU NUMBER</th>
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<th class="label">LUT NUMBER</th>
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<th class="label">DSP NUMBER</th>
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<th class="label">BSRAM NUMBER</th>
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<th class="label">SSRAM NUMBER</th>
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<th class="label">ROM16 NUMBER</th>
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</tr>
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<tr>
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<td class="label">BitM (C:/cygwin64/home/koray/verilog/lab2/src/BitM.v)</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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<td align = "center">3</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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<td align = "center">-</td>
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||||
</tr>
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||||
</table>
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||||
</div><!-- content -->
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||||
</div><!-- main_wrapper -->
|
||||
</body>
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||||
</html>
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||||
2
lab2/impl/gwsynthesis/lab2_syn_rsc.xml
Normal file
2
lab2/impl/gwsynthesis/lab2_syn_rsc.xml
Normal file
@ -0,0 +1,2 @@
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||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Module name="BitM" Lut="3" T_Lut="3(3)"/>
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||||
Reference in New Issue
Block a user