verilog

2024-04-13 05:48:55 +03:00
commit ed465dd690
61 changed files with 2719 additions and 0 deletions
--- a/hello.v
+++ b/hello.v
@@ -0,0 +1,9 @@
+module hello(
+	input wire A, B,
+	output wire C, D
+);
+
+and(D, A, B);
+xor(C, A, B);
+
+endmodule