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lab3

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k0rrluna
2024-12-12 01:05:57 +03:00
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iverilog/tobb/lab3/halfadder.v Normal file
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module halfadder (
input A, B,
output Sum, CarryOut
);
xor xor1(Sum, A, B);
and and1(CarryOut, A, B);
endmodule