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lab3

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k0rrluna
2024-12-12 01:05:57 +03:00
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commit cd93206ad4
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iverilog/tobb/lab3/fulladderTB.v Normal file
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module fulladderTB();
reg A, B, CarryIn;
wire Sum, CarryOut;
fulladder uut(
.A(A),
.B(B),
.CarryIn(CarryIn),
.Sum(Sum),
.CarryOut(CarryOut)
);
initial begin
$dumpfile("fulladder.vcd");
$dumpvars;
A = 1'b0; B = 1'b0; CarryIn = 1'b0; #10;
A = 1'b0; B = 1'b0; CarryIn = 1'b1; #10;
A = 1'b0; B = 1'b1; CarryIn = 1'b0; #10;
A = 1'b0; B = 1'b1; CarryIn = 1'b1; #10;
A = 1'b1; B = 1'b0; CarryIn = 1'b0; #10;
A = 1'b1; B = 1'b0; CarryIn = 1'b1; #10;
A = 1'b1; B = 1'b1; CarryIn = 1'b0; #10;
A = 1'b1; B = 1'b1; CarryIn = 1'b1; #10;
$finish;
end
endmodule