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lab3

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k0rrluna
2024-12-12 01:05:57 +03:00
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iverilog/tobb/lab3/fulladder.vcd Normal file
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$date
Thu Dec 12 00:41:38 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module fulladderTB $end
$var wire 1 ! Sum $end
$var wire 1 " CarryOut $end
$var reg 1 # A $end
$var reg 1 $ B $end
$var reg 1 % CarryIn $end
$scope module uut $end
$var wire 1 # A $end
$var wire 1 $ B $end
$var wire 1 % CarryIn $end
$var wire 1 " CarryOut $end
$var wire 1 ! Sum $end
$var wire 1 & AxorB $end
$var wire 1 ' AandB $end
$var wire 1 ( ABandCIn $end
$scope module h1 $end
$var wire 1 # A $end
$var wire 1 $ B $end
$var wire 1 ' CarryOut $end
$var wire 1 & Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 & A $end
$var wire 1 % B $end
$var wire 1 ( CarryOut $end
$var wire 1 ! Sum $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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$end
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