lab3

2024-12-12 01:05:57 +03:00
parent c1d75786ef
commit cd93206ad4
9 changed files with 706 additions and 0 deletions
--- a/iverilog/tobb/lab3/fulladder.v
+++ b/iverilog/tobb/lab3/fulladder.v
@ -0,0 +1,13 @@
+module fulladder (
+    input A, B, CarryIn,
+    output Sum, CarryOut
+);
+
+    wire AandB, AxorB, ABandCIn;
+
+    halfadder h1 (.A(A),.B(B),.Sum(AxorB), .CarryOut(AandB));
+    halfadder h2 (.A(AxorB), .B(CarryIn), .Sum(Sum), .CarryOut(ABandCIn));
+
+    or o1 (CarryOut, AandB, ABandCIn);
+
+endmodule