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lab3

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k0rrluna
2024-12-12 01:05:57 +03:00
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iverilog/tobb/lab3/bit3Adder.vcd Normal file
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$date
Thu Dec 12 01:03:03 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module bit3AdderTB $end
$var wire 4 ! Sum [3:0] $end
$var reg 3 " A [2:0] $end
$var reg 3 # B [2:0] $end
$scope module uut $end
$var wire 3 $ A [2:0] $end
$var wire 3 % B [2:0] $end
$var wire 4 & Sum [3:0] $end
$var wire 3 ' Carry3 [2:0] $end
$scope module f1 $end
$var wire 1 ( A $end
$var wire 1 ) B $end
$var wire 1 * CarryIn $end
$var wire 1 + CarryOut $end
$var wire 1 , Sum $end
$var wire 1 - AxorB $end
$var wire 1 . AandB $end
$var wire 1 / ABandCIn $end
$scope module h1 $end
$var wire 1 ( A $end
$var wire 1 ) B $end
$var wire 1 . CarryOut $end
$var wire 1 - Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 - A $end
$var wire 1 * B $end
$var wire 1 / CarryOut $end
$var wire 1 , Sum $end
$upscope $end
$upscope $end
$scope module f2 $end
$var wire 1 0 A $end
$var wire 1 1 B $end
$var wire 1 2 CarryIn $end
$var wire 1 3 CarryOut $end
$var wire 1 4 Sum $end
$var wire 1 5 AxorB $end
$var wire 1 6 AandB $end
$var wire 1 7 ABandCIn $end
$scope module h1 $end
$var wire 1 0 A $end
$var wire 1 1 B $end
$var wire 1 6 CarryOut $end
$var wire 1 5 Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 5 A $end
$var wire 1 2 B $end
$var wire 1 7 CarryOut $end
$var wire 1 4 Sum $end
$upscope $end
$upscope $end
$scope module h1 $end
$var wire 1 8 A $end
$var wire 1 9 B $end
$var wire 1 : CarryOut $end
$var wire 1 ; Sum $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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08
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06
05
04
03
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$end
#10
b1 !
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19
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#20
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bz01 '
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18
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#30
14
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12
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#40
b101 !
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19
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#50
13
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17
b1000 !
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15
09
10
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#60
02
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07
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16
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18
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#70
b1011 !
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#100