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ALU & multiplication

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k0rrluna 2024-12-21 18:05:27 +03:00
parent 25c2828592
commit c5af5cfeda
4 changed files with 3807 additions and 1428 deletions
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2421
project0.2/ALU
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34
project0.2/ALU.v
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@ -2,22 +2,24 @@ module ALU (
input [3:0] A, B,
input CarryIN,
input [2:0] opCodeA,
output [3:0] Y,
output [7:0] Y,
output CarryOUT, overflow
);
// Supports: ADD[0], SUB[1], AND[4], OR[5], XOR[6]
// Supports: ADD[0], SUB[1], MULT[2], AND[4], OR[5], XOR[6]
wire [7:0] opCode8;
wire [3:0] add_Y, sub_Y;
wire [3:0] resultA, resultO, resultX, lUOutput1;
wire [3:0] aUtemp1, aUtemp2, lUOutput2;
wire [3:0] wireY;
wire [3:0] wireY, wireLA;
wire [7:0] opwireM, wireM;
opCode opCd (.A(opCodeA), .opCode(opCode8));
arithmeticUnit aU(.opCode(opCode8[1:0]), .A(A), .B(B), .CarryIN(CarryIN), .add_Y(add_Y), .sub_Y(sub_Y), .CarryOUT(CarryOUT), .overflow(overflow));
logicUnit lU (.opCode(opCode8[6:4]), .A(A), .B(B), .resultA(resultA), .resultO(resultO), .resultX(resultX));
multiplier mU (.A(A), .B(B), .Y(opwireM));
or o01 (lUOutput1[0], resultA[0], resultO[0]);
or o02 (lUOutput1[1], resultA[1], resultO[1]);
@ -41,6 +43,15 @@ and a12 (aUtemp2[1], opCode8[1], sub_Y[1]);
and a13 (aUtemp2[2], opCode8[1], sub_Y[2]);
and a14 (aUtemp2[3], opCode8[1], sub_Y[3]);
and a21 (wireM[0], opCode8[2], opwireM[0]);
and a22 (wireM[1], opCode8[2], opwireM[1]);
and a23 (wireM[2], opCode8[2], opwireM[2]);
and a24 (wireM[3], opCode8[2], opwireM[3]);
and a25 (wireM[4], opCode8[2], opwireM[4]);
and a26 (wireM[5], opCode8[2], opwireM[5]);
and a27 (wireM[6], opCode8[2], opwireM[6]);
and a28 (wireM[7], opCode8[2], opwireM[7]);
or o21 (wireY[0], aUtemp1[0], aUtemp2[0]);
or o22 (wireY[1], aUtemp1[1], aUtemp2[1]);
@ -48,10 +59,19 @@ or o23 (wireY[2], aUtemp1[2], aUtemp2[2]);
or o24 (wireY[3], aUtemp1[3], aUtemp2[3]);
or o1 (Y[0], lUOutput2[0], wireY[0]);
or o2 (Y[1], lUOutput2[1], wireY[1]);
or o3 (Y[2], lUOutput2[2], wireY[2]);
or o4 (Y[3], lUOutput2[3], wireY[3]);
or o1 (wireLA[0], lUOutput2[0], wireY[0]);
or o2 (wireLA[1], lUOutput2[1], wireY[1]);
or o3 (wireLA[2], lUOutput2[2], wireY[2]);
or o4 (wireLA[3], lUOutput2[3], wireY[3]);
or o31 (Y[0], wireLA[0], wireM[0]);
or o32 (Y[1], wireLA[1], wireM[1]);
or o33 (Y[2], wireLA[2], wireM[2]);
or o34 (Y[3], wireLA[3], wireM[3]);
or o35 (Y[4], 1'b0, wireM[4]);
or o36 (Y[5], 1'b0, wireM[5]);
or o37 (Y[6], 1'b0, wireM[6]);
or o38 (Y[7], 1'b0, wireM[7]);
endmodule

2772
project0.2/ALU.vcd
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8
project0.2/ALUTB.v
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@ -3,7 +3,7 @@ module ALUTB ();
reg [3:0] A, B;
reg CarryIN;
reg [2:0] opCodeA;
wire [3:0] Y;
wire [7:0] Y;
wire CarryOUT, overflow;
ALU uut(
@ -30,6 +30,12 @@ initial begin
A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b001; #5;
A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b001; #5;
A = 4'b0111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b001; #5;
A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b010; #5;
A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b010; #5;
A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b010; #5;
A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b010; #5;
A = 4'b0111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b010; #5;
$finish; //NOT CONTAIN CLK, BUT STILL STOPS CODE
end