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verilog

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This commit is contained in:
k0rrluna
2024-07-05 19:15:16 +03:00
parent 492a55d360
commit c1f0851a45
136 changed files with 11599 additions and 0 deletions
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labs/lab3/impl/gwsynthesis/lab3_syn_rsc.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<Module name="mult2bit" Lut="1" T_Lut="4(1)">
<SubModule name="h0" Lut="1" T_Lut="1(1)"/>
<SubModule name="h1" Lut="2" T_Lut="2(2)"/>
</Module>