verilog/labs/lab3/impl/gwsynthesis/lab3_syn_rsc.xml
2024-07-05 19:15:16 +03:00

6 lines
191 B
XML

<?xml version="1.0" encoding="UTF-8"?>
<Module name="mult2bit" Lut="1" T_Lut="4(1)">
<SubModule name="h0" Lut="1" T_Lut="1(1)"/>
<SubModule name="h1" Lut="2" T_Lut="2(2)"/>
</Module>