verilog
This commit is contained in:
24
labs/lab2/impl/gwsynthesis/lab2.log
Normal file
24
labs/lab2/impl/gwsynthesis/lab2.log
Normal file
@ -0,0 +1,24 @@
|
||||
GowinSynthesis start
|
||||
Running parser ...
|
||||
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\BitM.v'
|
||||
Compiling module 'BitM'("C:\cygwin64\home\koray\verilog\lab2\src\BitM.v":1)
|
||||
NOTE (EX0101) : Current top module is "BitM"
|
||||
[5%] Running netlist conversion ...
|
||||
Running device independent optimization ...
|
||||
[10%] Optimizing Phase 0 completed
|
||||
[15%] Optimizing Phase 1 completed
|
||||
[25%] Optimizing Phase 2 completed
|
||||
Running inference ...
|
||||
[30%] Inferring Phase 0 completed
|
||||
[40%] Inferring Phase 1 completed
|
||||
[50%] Inferring Phase 2 completed
|
||||
[55%] Inferring Phase 3 completed
|
||||
Running technical mapping ...
|
||||
[60%] Tech-Mapping Phase 0 completed
|
||||
[65%] Tech-Mapping Phase 1 completed
|
||||
[75%] Tech-Mapping Phase 2 completed
|
||||
[80%] Tech-Mapping Phase 3 completed
|
||||
[90%] Tech-Mapping Phase 4 completed
|
||||
[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg" completed
|
||||
[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2_syn.rpt.html" completed
|
||||
GowinSynthesis finish
|
||||
19
labs/lab2/impl/gwsynthesis/lab2.prj
Normal file
19
labs/lab2/impl/gwsynthesis/lab2.prj
Normal file
@ -0,0 +1,19 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE gowin-synthesis-project>
|
||||
<Project>
|
||||
<Version>beta</Version>
|
||||
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
|
||||
<FileList>
|
||||
<File path="C:\cygwin64\home\koray\verilog\lab2\src\BitM.v" type="verilog"/>
|
||||
</FileList>
|
||||
<OptionList>
|
||||
<Option type="disable_insert_pad" value="0"/>
|
||||
<Option type="global_freq" value="100.000"/>
|
||||
<Option type="looplimit" value="2000"/>
|
||||
<Option type="output_file" value="C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg"/>
|
||||
<Option type="print_all_synthesis_warning" value="0"/>
|
||||
<Option type="ram_rw_check" value="0"/>
|
||||
<Option type="verilog_language" value="verilog-2001"/>
|
||||
<Option type="vhdl_language" value="vhdl-1993"/>
|
||||
</OptionList>
|
||||
</Project>
|
||||
76
labs/lab2/impl/gwsynthesis/lab2.vg
Normal file
76
labs/lab2/impl/gwsynthesis/lab2.vg
Normal file
@ -0,0 +1,76 @@
|
||||
//
|
||||
//Written by GowinSynthesis
|
||||
//Tool Version "V1.9.9.02"
|
||||
//Thu Apr 11 07:46:56 2024
|
||||
|
||||
//Source file index table:
|
||||
//file0 "\C:/cygwin64/home/koray/verilog/lab2/src/BitM.v"
|
||||
`timescale 100 ps/100 ps
|
||||
module BitM (
|
||||
A,
|
||||
B,
|
||||
AlB,
|
||||
AeB,
|
||||
AgB
|
||||
)
|
||||
;
|
||||
input A;
|
||||
input B;
|
||||
output AlB;
|
||||
output AeB;
|
||||
output AgB;
|
||||
wire A_d;
|
||||
wire B_d;
|
||||
wire AlB_d;
|
||||
wire AgB_d;
|
||||
wire AeB_d;
|
||||
wire VCC;
|
||||
wire GND;
|
||||
IBUF A_ibuf (
|
||||
.O(A_d),
|
||||
.I(A)
|
||||
);
|
||||
IBUF B_ibuf (
|
||||
.O(B_d),
|
||||
.I(B)
|
||||
);
|
||||
OBUF AlB_obuf (
|
||||
.O(AlB),
|
||||
.I(AlB_d)
|
||||
);
|
||||
OBUF AeB_obuf (
|
||||
.O(AeB),
|
||||
.I(AeB_d)
|
||||
);
|
||||
OBUF AgB_obuf (
|
||||
.O(AgB),
|
||||
.I(AgB_d)
|
||||
);
|
||||
LUT2 AlB_d_s (
|
||||
.F(AlB_d),
|
||||
.I0(A_d),
|
||||
.I1(B_d)
|
||||
);
|
||||
defparam AlB_d_s.INIT=4'h4;
|
||||
LUT2 AgB_d_s (
|
||||
.F(AgB_d),
|
||||
.I0(B_d),
|
||||
.I1(A_d)
|
||||
);
|
||||
defparam AgB_d_s.INIT=4'h4;
|
||||
LUT2 AeB_d_s (
|
||||
.F(AeB_d),
|
||||
.I0(A_d),
|
||||
.I1(B_d)
|
||||
);
|
||||
defparam AeB_d_s.INIT=4'h9;
|
||||
VCC VCC_cZ (
|
||||
.V(VCC)
|
||||
);
|
||||
GND GND_cZ (
|
||||
.G(GND)
|
||||
);
|
||||
GSR GSR (
|
||||
.GSRI(VCC)
|
||||
);
|
||||
endmodule /* BitM */
|
||||
167
labs/lab2/impl/gwsynthesis/lab2_syn.rpt.html
Normal file
167
labs/lab2/impl/gwsynthesis/lab2_syn.rpt.html
Normal file
@ -0,0 +1,167 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>synthesis Report</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
div#content { margin-left: 350px; margin-right: 30px; }
|
||||
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
|
||||
div#catalog ul { list-style-type: none; }
|
||||
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
|
||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
|
||||
div#catalog a:visited { color: #0084ff; }
|
||||
div#catalog a:hover { color: #fff; background: #0084ff; }
|
||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
||||
h1, h3 { text-align: center; }
|
||||
h1 {margin-top: 50px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { padding: 5px 5px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.detail_table td.label { min-width: 100px; width: 8%;}
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="catalog_wrapper">
|
||||
<div id="catalog">
|
||||
<ul>
|
||||
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
|
||||
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
|
||||
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
|
||||
<ul>
|
||||
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
|
||||
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
<div id="content">
|
||||
<h1><a name="about">Synthesis Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>GowinSynthesis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\cygwin64\home\koray\verilog\lab2\src\BitM.v<br>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">GowinSynthesis Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.9.02</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device Version</td>
|
||||
<td>C</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Thu Apr 11 07:46:56 2024
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="summary">Synthesis Details</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Top Level Module</td>
|
||||
<td>BitM</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Synthesis Process</td>
|
||||
<td>Running parser:<br/> CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 181.887MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.132s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>Generate output files:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 181.887MB<br/></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Total Time and Memory Usage</td>
|
||||
<td>CPU time = 0h 0m 0.108s, Elapsed time = 0h 0m 0.221s, Peak memory usage = 181.887MB</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="resource">Resource</a></h1>
|
||||
<h2><a name="usage">Resource Usage Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Port </b></td>
|
||||
<td>5</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Buf </b></td>
|
||||
<td>5</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    IBUF</td>
|
||||
<td>2</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    OBUF</td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>LUT </b></td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT2</td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="utilization">Resource Utilization Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
<td><b>Utilization</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Logic</td>
|
||||
<td>3(3 LUT, 0 ALU) / 20736</td>
|
||||
<td><1%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Register</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as Latch</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as FF</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">BSRAM</td>
|
||||
<td>0 / 46</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
46
labs/lab2/impl/gwsynthesis/lab2_syn_resource.html
Normal file
46
labs/lab2/impl/gwsynthesis/lab2_syn_resource.html
Normal file
@ -0,0 +1,46 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Hierarchy Module Resource</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
h1 {text-align: center; }
|
||||
h1 {margin-top: 36px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { align = "center"; padding: 5px 2px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="content">
|
||||
<h1>Hierarchy Module Resource</h1>
|
||||
<table>
|
||||
<tr>
|
||||
<th class="label">MODULE NAME</th>
|
||||
<th class="label">REG NUMBER</th>
|
||||
<th class="label">ALU NUMBER</th>
|
||||
<th class="label">LUT NUMBER</th>
|
||||
<th class="label">DSP NUMBER</th>
|
||||
<th class="label">BSRAM NUMBER</th>
|
||||
<th class="label">SSRAM NUMBER</th>
|
||||
<th class="label">ROM16 NUMBER</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">BitM (C:/cygwin64/home/koray/verilog/lab2/src/BitM.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">3</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
2
labs/lab2/impl/gwsynthesis/lab2_syn_rsc.xml
Normal file
2
labs/lab2/impl/gwsynthesis/lab2_syn_rsc.xml
Normal file
@ -0,0 +1,2 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Module name="BitM" Lut="3" T_Lut="3(3)"/>
|
||||
Reference in New Issue
Block a user