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nand2tetris

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k0rrluna
2024-12-10 01:25:05 +03:00
parent 2acbfd9d8d
commit c1d75786ef
31 changed files with 1058 additions and 24 deletions
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20
iverilog/nand2tetris/nands/not/notGateTB.v Normal file
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module notGateTB;
reg A_i;
wire B_o;
notGate uut (
.A_i(A_i),
.B_o(B_o)
);
initial begin
$dumpfile("notGate.vcd");
$dumpvars;
A_i = 1'b0;
#10;
A_i = 1'b1;
#10;
$finish;
end
endmodule