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nand2tetris

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k0rrluna
2024-12-10 01:25:05 +03:00
parent 2acbfd9d8d
commit c1d75786ef
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iverilog/nand2tetris/nands/not/notGate.v Normal file
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module notGate (
input A_i,
output B_o
);
nand nand1 (B_o, A_i, A_i);
endmodule