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nand2tetris

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This commit is contained in:
k0rrluna
2024-12-10 01:25:05 +03:00
parent 2acbfd9d8d
commit c1d75786ef
31 changed files with 1058 additions and 24 deletions
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73
iverilog/nand2tetris/nands/mux/muxGate Normal file
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#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55620be3ed30 .scope module, "muxGateTB" "muxGateTB" 2 1;
.timescale 0 0;
v0x55620be51410_0 .var "A_i", 0 0;
v0x55620be514d0_0 .var "B_i", 0 0;
v0x55620be515a0_0 .var "S_i", 0 0;
v0x55620be516a0_0 .net "Y_o", 0 0, L_0x55620be519e0; 1 drivers
S_0x55620be3eec0 .scope module, "uut" "muxGate" 2 5, 3 1 0, S_0x55620be3ed30;
.timescale 0 0;
.port_info 0 /INPUT 1 "A_i";
.port_info 1 /INPUT 1 "B_i";
.port_info 2 /INPUT 1 "S_i";
.port_info 3 /OUTPUT 1 "Y_o";
L_0x55620be51770 .functor NAND 1, v0x55620be515a0_0, v0x55620be515a0_0, C4<1>, C4<1>;
L_0x55620be51860 .functor NAND 1, v0x55620be51410_0, v0x55620be515a0_0, C4<1>, C4<1>;
L_0x55620be51920 .functor NAND 1, v0x55620be514d0_0, L_0x55620be51770, C4<1>, C4<1>;
L_0x55620be519e0 .functor NAND 1, L_0x55620be51860, L_0x55620be51920, C4<1>, C4<1>;
v0x55620be2c2e0_0 .net "A_i", 0 0, v0x55620be51410_0; 1 drivers
v0x55620be50eb0_0 .net "B_i", 0 0, v0x55620be514d0_0; 1 drivers
v0x55620be50f70_0 .net "S_i", 0 0, v0x55620be515a0_0; 1 drivers
v0x55620be51040_0 .net "Y_o", 0 0, L_0x55620be519e0; alias, 1 drivers
v0x55620be51100_0 .net "nand2_out", 0 0, L_0x55620be51860; 1 drivers
v0x55620be51210_0 .net "nand3_out", 0 0, L_0x55620be51920; 1 drivers
v0x55620be512d0_0 .net "notS", 0 0, L_0x55620be51770; 1 drivers
.scope S_0x55620be3ed30;
T_0 ;
%vpi_call 2 13 "$dumpfile", "muxGate.vcd" {0 0 0};
%vpi_call 2 14 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55620be51410_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55620be514d0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55620be515a0_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55620be51410_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55620be514d0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55620be515a0_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55620be51410_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55620be514d0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55620be515a0_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55620be51410_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55620be514d0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55620be515a0_0, 0, 1;
%delay 10, 0;
%vpi_call 2 19 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"muxGateTB.v";
"muxGate.v";

15
iverilog/nand2tetris/nands/mux/muxGate.v Normal file
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module muxGate (
input A_i, B_i, S_i,
output Y_o
);
wire notS,nand2_out,nand3_out;
nand nand1(notS, S_i, S_i);
nand nand2(nand2_out, A_i, S_i);
nand nand3(nand3_out, B_i, notS);
nand nand4(Y_o, nand2_out, nand3_out);
endmodule

48
iverilog/nand2tetris/nands/mux/muxGate.vcd Normal file
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$date
Tue Dec 10 00:01:05 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module muxGateTB $end
$var wire 1 ! Y_o $end
$var reg 1 " A_i $end
$var reg 1 # B_i $end
$var reg 1 $ S_i $end
$scope module uut $end
$var wire 1 " A_i $end
$var wire 1 # B_i $end
$var wire 1 $ S_i $end
$var wire 1 ! Y_o $end
$var wire 1 % nand2_out $end
$var wire 1 & nand3_out $end
$var wire 1 ' notS $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1'
0&
1%
0$
1#
0"
1!
$end
#10
0!
1&
0#
1"
#20
0!
0'
1&
1$
1#
0"
#40

22
iverilog/nand2tetris/nands/mux/muxGateTB.v Normal file
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module muxGateTB();
reg A_i, B_i, S_i;
wire Y_o;
muxGate uut(
.A_i(A_i),
.B_i(B_i),
.S_i(S_i),
.Y_o(Y_o)
);
initial begin
$dumpfile("muxGate.vcd");
$dumpvars;
A_i = 1'b0; B_i = 1'b1; S_i = 1'b0; #10;
A_i = 1'b1; B_i = 1'b0; S_i = 1'b0; #10;
A_i = 1'b0; B_i = 1'b1; S_i = 1'b1; #10;
A_i = 1'b0; B_i = 1'b1; S_i = 1'b1; #10;
$finish;
end
endmodule