nand2tetris

iverilog/nand2tetris/nands/dmux/dmuxGate.vcd

@@ -0,0 +1,50 @@
+$date
+	Tue Dec 10 00:15:58 2024
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module dmuxGateTB $end
+$var wire 1 ! Y1_o $end
+$var wire 1 " Y0_o $end
+$var reg 1 # A_i $end
+$var reg 1 $ S_i $end
+$scope module uut $end
+$var wire 1 # A_i $end
+$var wire 1 $ S_i $end
+$var wire 1 " Y0_o $end
+$var wire 1 ! Y1_o $end
+$var wire 1 % nand2_out $end
+$var wire 1 & nand4_out $end
+$var wire 1 ' notS $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+1'
+1&
+1%
+0$
+0#
+0"
+0!
+$end
+#10
+1"
+0%
+1#
+#20
+0"
+0'
+1%
+1$
+0#
+#30
+1!
+0&
+1#
+#40