opCode fixes

project/opCode.vcd

@@ -1,5 +1,5 @@
 $date
-	Sun Dec 15 00:28:47 2024
+	Sun Dec 15 04:12:35 2024
 $end
 $version
 	Icarus Verilog
@@ -9,86 +9,84 @@ $timescale
 $end
 $scope module opCodeTB $end
 $var wire 8 ! opCode [7:0] $end
-$var reg 1 " A $end
-$var reg 1 # B $end
-$var reg 1 $ C $end
+$var reg 3 " A [2:0] $end
 $scope module uut $end
-$var wire 1 " A $end
-$var wire 1 # B $end
-$var wire 1 $ C $end
-$var wire 1 % and1 $end
-$var wire 1 & and2 $end
-$var wire 1 ' and3 $end
-$var wire 1 ( and4 $end
-$var wire 1 ) notA $end
-$var wire 1 * notB $end
-$var wire 1 + notC $end
-$var wire 8 , opCode [7:0] $end
+$var wire 3 # A [2:0] $end
+$var wire 1 $ and1 $end
+$var wire 1 % and2 $end
+$var wire 1 & and3 $end
+$var wire 1 ' and4 $end
+$var wire 1 ( notA $end
+$var wire 1 ) notB $end
+$var wire 1 * notC $end
+$var wire 8 + opCode [7:0] $end
 $upscope $end
 $upscope $end
 $enddefinitions $end
 #0
 $dumpvars
-b1 ,
-1+
+b1 +
 1*
 1)
 1(
-0'
+1'
 0&
 0%
 0$
-0#
-0"
+b0 #
+b0 "
 b1 !
 $end
 #3
-0+
-b10 !
-b10 ,
-1$
-#6
-0(
-1+
-b100 !
-b100 ,
 0*
-1&
-0$
-1#
-#9
-0+
-b1000 !
-b1000 ,
-1$
-#12
-1'
-1+
-b10000 !
-b10000 ,
+b10 !
+b10 +
+b1 "
+b1 #
+#6
+0'
+0)
 1*
+1%
+b100 !
+b100 +
+b10 "
+b10 #
+#9
+0*
+b1000 !
+b1000 +
+b11 "
+b11 #
+#12
+1&
+0(
+1)
+1*
+0%
+b10000 !
+b10000 +
+b100 "
+b100 #
+#15
+0*
+b100000 !
+b100000 +
+b101 "
+b101 #
+#18
 0&
 0)
-0$
-0#
-1"
-#15
-0+
-b100000 !
-b100000 ,
+1*
 1$
-#18
-0'
-1+
 b1000000 !
-b1000000 ,
-0*
-1%
-0$
-1#
+b1000000 +
+b110 "
+b110 #
 #21
-0+
+0*
 b10000000 !
-b10000000 ,
-1$
+b10000000 +
+b111 "
+b111 #
 #24