lab5

iverilog/tobb/lab5/ayarliSayac.vcd

@@ -0,0 +1,155 @@
+$date
+	Sat Jan 25 07:58:46 2025
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module ayarliSayacTB $end
+$var wire 6 ! sayac [5:0] $end
+$var reg 1 " clk $end
+$var reg 1 # en $end
+$var reg 1 $ rst $end
+$var reg 3 % sayma_miktari [2:0] $end
+$var reg 1 & sayma_yonu $end
+$scope module uut $end
+$var wire 1 " clk $end
+$var wire 1 # en $end
+$var wire 1 $ rst $end
+$var wire 3 ' sayma_miktari [2:0] $end
+$var wire 1 & sayma_yonu $end
+$var reg 2 ( clk_divider [1:0] $end
+$var reg 3 ) miktar [2:0] $end
+$var reg 6 * sayac [5:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b0 *
+b1 )
+b1 (
+b110 '
+1&
+b110 %
+0$
+1#
+0"
+b0 !
+$end
+#1
+1"
+#2
+b10 (
+0"
+#3
+1"
+#4
+b11 (
+0"
+#5
+1"
+#6
+b1 !
+b1 *
+b110 )
+b0 (
+0"
+#7
+1"
+#8
+b1 (
+0"
+#9
+1"
+#10
+b10 (
+0"
+#11
+1"
+#12
+b11 (
+0"
+#13
+1"
+#14
+b111 !
+b111 *
+b0 (
+0"
+#15
+1"
+#16
+b1 (
+0"
+b10 %
+b10 '
+0#
+#17
+1"
+#18
+b10 (
+0"
+#19
+1"
+#20
+b11 (
+0"
+#21
+1"
+#22
+b0 (
+0"
+#23
+1"
+#24
+b1 (
+0"
+b11 %
+b11 '
+1#
+#25
+1"
+#26
+b10 (
+0"
+#27
+1"
+#28
+b11 (
+0"
+#29
+1"
+#30
+b1101 !
+b1101 *
+b11 )
+b0 (
+0"
+#31
+1"
+#32
+b0 !
+b0 *
+0"
+b10 %
+b10 '
+1$
+#33
+1"
+#34
+0"
+#35
+1"
+#36
+0"
+#37
+1"
+#38
+0"
+#39
+1"
+#40
+0"