diff --git a/iverilog/tobb/lab5/ayarliSayac b/iverilog/tobb/lab5/ayarliSayac
new file mode 100644
index 0000000..6841014
--- /dev/null
+++ b/iverilog/tobb/lab5/ayarliSayac
@@ -0,0 +1,180 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x55ffcf0ba4e0 .scope module, "ayarliSayacTB" "ayarliSayacTB" 2 1;
+ .timescale 0 0;
+v0x55ffcf0d1530_0 .var "clk", 0 0;
+v0x55ffcf0d15f0_0 .var "en", 0 0;
+v0x55ffcf0d16c0_0 .var "rst", 0 0;
+v0x55ffcf0d17c0_0 .net "sayac", 5 0, v0x55ffcf0d11f0_0;  1 drivers
+v0x55ffcf0d1890_0 .var "sayma_miktari", 2 0;
+v0x55ffcf0d1980_0 .var "sayma_yonu", 0 0;
+S_0x55ffcf0ba670 .scope module, "uut" "ayarliSayac" 2 8, 3 1 0, S_0x55ffcf0ba4e0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "en";
+    .port_info 3 /INPUT 3 "sayma_miktari";
+    .port_info 4 /INPUT 1 "sayma_yonu";
+    .port_info 5 /OUTPUT 6 "sayac";
+v0x55ffcf0a5c70_0 .net "clk", 0 0, v0x55ffcf0d1530_0;  1 drivers
+v0x55ffcf0d0e80_0 .var "clk_divider", 1 0;
+v0x55ffcf0d0f60_0 .net "en", 0 0, v0x55ffcf0d15f0_0;  1 drivers
+v0x55ffcf0d1000_0 .var "miktar", 2 0;
+v0x55ffcf0d10e0_0 .net "rst", 0 0, v0x55ffcf0d16c0_0;  1 drivers
+v0x55ffcf0d11f0_0 .var "sayac", 5 0;
+v0x55ffcf0d12d0_0 .net "sayma_miktari", 2 0, v0x55ffcf0d1890_0;  1 drivers
+v0x55ffcf0d13b0_0 .net "sayma_yonu", 0 0, v0x55ffcf0d1980_0;  1 drivers
+E_0x55ffcf0b4e60/0 .event negedge, v0x55ffcf0a5c70_0;
+E_0x55ffcf0b4e60/1 .event posedge, v0x55ffcf0d10e0_0;
+E_0x55ffcf0b4e60 .event/or E_0x55ffcf0b4e60/0, E_0x55ffcf0b4e60/1;
+    .scope S_0x55ffcf0ba670;
+T_0 ;
+    %pushi/vec4 0, 0, 6;
+    %store/vec4 v0x55ffcf0d11f0_0, 0, 6;
+    %pushi/vec4 1, 0, 3;
+    %store/vec4 v0x55ffcf0d1000_0, 0, 3;
+    %pushi/vec4 0, 0, 2;
+    %store/vec4 v0x55ffcf0d0e80_0, 0, 2;
+    %end;
+    .thread T_0;
+    .scope S_0x55ffcf0ba670;
+T_1 ;
+    %wait E_0x55ffcf0b4e60;
+    %load/vec4 v0x55ffcf0d10e0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.0, 8;
+    %pushi/vec4 0, 0, 6;
+    %assign/vec4 v0x55ffcf0d11f0_0, 0;
+    %pushi/vec4 0, 0, 2;
+    %assign/vec4 v0x55ffcf0d0e80_0, 0;
+    %jmp T_1.1;
+T_1.0 ;
+    %load/vec4 v0x55ffcf0d0e80_0;
+    %addi 1, 0, 2;
+    %assign/vec4 v0x55ffcf0d0e80_0, 0;
+T_1.1 ;
+    %load/vec4 v0x55ffcf0d0e80_0;
+    %cmpi/e 3, 0, 2;
+    %jmp/0xz  T_1.2, 4;
+    %load/vec4 v0x55ffcf0d0f60_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.4, 8;
+    %load/vec4 v0x55ffcf0d12d0_0;
+    %assign/vec4 v0x55ffcf0d1000_0, 0;
+    %load/vec4 v0x55ffcf0d13b0_0;
+    %pad/u 32;
+    %cmpi/e 1, 0, 32;
+    %jmp/0xz  T_1.6, 4;
+    %load/vec4 v0x55ffcf0d11f0_0;
+    %load/vec4 v0x55ffcf0d1000_0;
+    %pad/u 6;
+    %add;
+    %cmpi/u 63, 0, 6;
+    %flag_inv 5; GE is !LT
+    %jmp/0xz  T_1.8, 5;
+    %pushi/vec4 63, 0, 6;
+    %assign/vec4 v0x55ffcf0d11f0_0, 0;
+    %jmp T_1.9;
+T_1.8 ;
+    %load/vec4 v0x55ffcf0d1000_0;
+    %pad/u 6;
+    %load/vec4 v0x55ffcf0d11f0_0;
+    %add;
+    %assign/vec4 v0x55ffcf0d11f0_0, 0;
+T_1.9 ;
+    %jmp T_1.7;
+T_1.6 ;
+    %load/vec4 v0x55ffcf0d11f0_0;
+    %load/vec4 v0x55ffcf0d1000_0;
+    %pad/u 6;
+    %sub;
+    %cmpi/u 0, 0, 6;
+    %flag_or 5, 4;
+    %jmp/0xz  T_1.10, 5;
+    %pushi/vec4 0, 0, 6;
+    %assign/vec4 v0x55ffcf0d11f0_0, 0;
+    %jmp T_1.11;
+T_1.10 ;
+    %load/vec4 v0x55ffcf0d11f0_0;
+    %load/vec4 v0x55ffcf0d1000_0;
+    %pad/u 6;
+    %sub;
+    %assign/vec4 v0x55ffcf0d11f0_0, 0;
+T_1.11 ;
+T_1.7 ;
+T_1.4 ;
+T_1.2 ;
+    %jmp T_1;
+    .thread T_1;
+    .scope S_0x55ffcf0ba4e0;
+T_2 ;
+    %load/vec4 v0x55ffcf0d1530_0;
+    %inv;
+    %store/vec4 v0x55ffcf0d1530_0, 0, 1;
+    %delay 1, 0;
+    %jmp T_2;
+    .thread T_2;
+    .scope S_0x55ffcf0ba4e0;
+T_3 ;
+    %vpi_call 2 22 "$dumpfile", "ayarliSayac.vcd" {0 0 0};
+    %vpi_call 2 23 "$dumpvars" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x55ffcf0d1530_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x55ffcf0d16c0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55ffcf0d15f0_0, 0, 1;
+    %pushi/vec4 6, 0, 3;
+    %store/vec4 v0x55ffcf0d1890_0, 0, 3;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55ffcf0d1980_0, 0, 1;
+    %delay 16, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55ffcf0d1530_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x55ffcf0d16c0_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x55ffcf0d15f0_0, 0, 1;
+    %pushi/vec4 2, 0, 3;
+    %store/vec4 v0x55ffcf0d1890_0, 0, 3;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55ffcf0d1980_0, 0, 1;
+    %delay 8, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55ffcf0d1530_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x55ffcf0d16c0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55ffcf0d15f0_0, 0, 1;
+    %pushi/vec4 3, 0, 3;
+    %store/vec4 v0x55ffcf0d1890_0, 0, 3;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55ffcf0d1980_0, 0, 1;
+    %delay 8, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55ffcf0d1530_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55ffcf0d16c0_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55ffcf0d15f0_0, 0, 1;
+    %pushi/vec4 2, 0, 3;
+    %store/vec4 v0x55ffcf0d1890_0, 0, 3;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x55ffcf0d1980_0, 0, 1;
+    %delay 8, 0;
+    %vpi_call 2 28 "$finish" {0 0 0};
+    %end;
+    .thread T_3;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "ayarliSayacTB.v";
+    "ayarliSayac.v";
diff --git a/iverilog/tobb/lab5/ayarliSayac.v b/iverilog/tobb/lab5/ayarliSayac.v
new file mode 100644
index 0000000..c80a265
--- /dev/null
+++ b/iverilog/tobb/lab5/ayarliSayac.v
@@ -0,0 +1,43 @@
+module ayarliSayac (
+    input clk, rst, en,
+    input [2:0] sayma_miktari,
+    input sayma_yonu,
+    output reg [5:0] sayac
+);
+
+    reg [2:0] miktar;
+    reg [1:0] clk_divider;
+
+    initial begin
+        sayac = 6'b0000_00;
+        miktar = 3'b001;
+        clk_divider = 2'b00;
+    end
+
+    always @(negedge clk or posedge rst) begin
+        if (rst) begin
+            sayac <= 6'b0000_00;
+            clk_divider <= 2'b00;
+        end else begin
+            clk_divider <= clk_divider + 1;
+        end
+        if (clk_divider == 2'b11) begin
+            if (en) begin
+            miktar <= sayma_miktari;
+            if (sayma_yonu == 1) begin
+                if (sayac + miktar >= 6'b1111_11) begin
+                    sayac <= 6'b1111_11;
+                end else begin
+                    sayac <= miktar + sayac;
+                end
+            end else begin
+                if (sayac - miktar <= 6'b0000_00) begin
+                    sayac <= 6'b0000_00;
+                end else begin
+                    sayac <= sayac - miktar;
+                end
+            end
+        end
+    end
+end
+endmodule
diff --git a/iverilog/tobb/lab5/ayarliSayac.vcd b/iverilog/tobb/lab5/ayarliSayac.vcd
new file mode 100644
index 0000000..c496b7b
--- /dev/null
+++ b/iverilog/tobb/lab5/ayarliSayac.vcd
@@ -0,0 +1,155 @@
+$date
+	Sat Jan 25 07:58:46 2025
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module ayarliSayacTB $end
+$var wire 6 ! sayac [5:0] $end
+$var reg 1 " clk $end
+$var reg 1 # en $end
+$var reg 1 $ rst $end
+$var reg 3 % sayma_miktari [2:0] $end
+$var reg 1 & sayma_yonu $end
+$scope module uut $end
+$var wire 1 " clk $end
+$var wire 1 # en $end
+$var wire 1 $ rst $end
+$var wire 3 ' sayma_miktari [2:0] $end
+$var wire 1 & sayma_yonu $end
+$var reg 2 ( clk_divider [1:0] $end
+$var reg 3 ) miktar [2:0] $end
+$var reg 6 * sayac [5:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b0 *
+b1 )
+b1 (
+b110 '
+1&
+b110 %
+0$
+1#
+0"
+b0 !
+$end
+#1
+1"
+#2
+b10 (
+0"
+#3
+1"
+#4
+b11 (
+0"
+#5
+1"
+#6
+b1 !
+b1 *
+b110 )
+b0 (
+0"
+#7
+1"
+#8
+b1 (
+0"
+#9
+1"
+#10
+b10 (
+0"
+#11
+1"
+#12
+b11 (
+0"
+#13
+1"
+#14
+b111 !
+b111 *
+b0 (
+0"
+#15
+1"
+#16
+b1 (
+0"
+b10 %
+b10 '
+0#
+#17
+1"
+#18
+b10 (
+0"
+#19
+1"
+#20
+b11 (
+0"
+#21
+1"
+#22
+b0 (
+0"
+#23
+1"
+#24
+b1 (
+0"
+b11 %
+b11 '
+1#
+#25
+1"
+#26
+b10 (
+0"
+#27
+1"
+#28
+b11 (
+0"
+#29
+1"
+#30
+b1101 !
+b1101 *
+b11 )
+b0 (
+0"
+#31
+1"
+#32
+b0 !
+b0 *
+0"
+b10 %
+b10 '
+1$
+#33
+1"
+#34
+0"
+#35
+1"
+#36
+0"
+#37
+1"
+#38
+0"
+#39
+1"
+#40
+0"
diff --git a/iverilog/tobb/lab5/ayarliSayacTB.v b/iverilog/tobb/lab5/ayarliSayacTB.v
new file mode 100644
index 0000000..c73d385
--- /dev/null
+++ b/iverilog/tobb/lab5/ayarliSayacTB.v
@@ -0,0 +1,31 @@
+module ayarliSayacTB();
+
+    reg clk, rst, en;
+    reg [2:0] sayma_miktari;
+    reg sayma_yonu;
+    wire [5:0] sayac;
+
+ayarliSayac uut (
+    .clk(clk),
+    .rst(rst),
+    .en(en),
+    .sayma_miktari(sayma_miktari),
+    .sayma_yonu(sayma_yonu),
+    .sayac(sayac)
+);
+
+always begin
+    clk = ~clk; #1;
+end
+
+initial begin
+    $dumpfile("ayarliSayac.vcd");
+    $dumpvars;
+    clk = 0; rst = 0; en = 1; sayma_miktari = 3'b110; sayma_yonu = 1'b1; #16;
+    clk = 1; rst = 0; en = 0; sayma_miktari = 3'b010; sayma_yonu = 1'b1; #8;
+    clk = 1; rst = 0; en = 1; sayma_miktari = 3'b011; sayma_yonu = 1'b1; #8;
+    clk = 1; rst = 1; en = 1; sayma_miktari = 3'b010; sayma_yonu = 1'b1; #8;
+    $finish;
+end
+
+endmodule
diff --git a/iverilog/tobb/lab5/knightRider b/iverilog/tobb/lab5/knightRider
new file mode 100644
index 0000000..80cb523
--- /dev/null
+++ b/iverilog/tobb/lab5/knightRider
@@ -0,0 +1,101 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x55c07fb12c40 .scope module, "knightRiderTB" "knightRiderTB" 2 1;
+ .timescale 0 0;
+v0x55c07fb24010_0 .var "clk", 0 0;
+v0x55c07fb240e0_0 .net "leds", 7 0, v0x55c07fb23ef0_0;  1 drivers
+S_0x55c07fb12dd0 .scope module, "uut" "knightRider" 2 6, 3 1 0, S_0x55c07fb12c40;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /OUTPUT 8 "leds";
+v0x55c07fad87f0_0 .net "clk", 0 0, v0x55c07fb24010_0;  1 drivers
+v0x55c07fad8c00_0 .var "direction", 0 0;
+v0x55c07fb23ef0_0 .var "leds", 7 0;
+E_0x55c07fad7810 .event posedge, v0x55c07fad87f0_0;
+    .scope S_0x55c07fb12dd0;
+T_0 ;
+    %pushi/vec4 7, 0, 8;
+    %store/vec4 v0x55c07fb23ef0_0, 0, 8;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x55c07fad8c00_0, 0, 1;
+    %end;
+    .thread T_0;
+    .scope S_0x55c07fb12dd0;
+T_1 ;
+    %wait E_0x55c07fad7810;
+    %load/vec4 v0x55c07fad8c00_0;
+    %pad/u 32;
+    %cmpi/e 0, 0, 32;
+    %jmp/0xz  T_1.0, 4;
+    %load/vec4 v0x55c07fb23ef0_0;
+    %cmpi/e 224, 0, 8;
+    %jmp/0xz  T_1.2, 4;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0x55c07fad8c00_0, 0;
+    %load/vec4 v0x55c07fb23ef0_0;
+    %ix/load 4, 1, 0;
+    %flag_set/imm 4, 0;
+    %shiftr 4;
+    %assign/vec4 v0x55c07fb23ef0_0, 0;
+    %jmp T_1.3;
+T_1.2 ;
+    %load/vec4 v0x55c07fb23ef0_0;
+    %ix/load 4, 1, 0;
+    %flag_set/imm 4, 0;
+    %shiftl 4;
+    %assign/vec4 v0x55c07fb23ef0_0, 0;
+T_1.3 ;
+    %jmp T_1.1;
+T_1.0 ;
+    %load/vec4 v0x55c07fb23ef0_0;
+    %cmpi/e 7, 0, 8;
+    %jmp/0xz  T_1.4, 4;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0x55c07fad8c00_0, 0;
+    %load/vec4 v0x55c07fb23ef0_0;
+    %ix/load 4, 1, 0;
+    %flag_set/imm 4, 0;
+    %shiftl 4;
+    %assign/vec4 v0x55c07fb23ef0_0, 0;
+    %jmp T_1.5;
+T_1.4 ;
+    %load/vec4 v0x55c07fb23ef0_0;
+    %ix/load 4, 1, 0;
+    %flag_set/imm 4, 0;
+    %shiftr 4;
+    %assign/vec4 v0x55c07fb23ef0_0, 0;
+T_1.5 ;
+T_1.1 ;
+    %jmp T_1;
+    .thread T_1;
+    .scope S_0x55c07fb12c40;
+T_2 ;
+    %load/vec4 v0x55c07fb24010_0;
+    %inv;
+    %store/vec4 v0x55c07fb24010_0, 0, 1;
+    %delay 2, 0;
+    %jmp T_2;
+    .thread T_2;
+    .scope S_0x55c07fb12c40;
+T_3 ;
+    %vpi_call 2 16 "$dumpfile", "knightRider.vcd" {0 0 0};
+    %vpi_call 2 17 "$dumpvars" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x55c07fb24010_0, 0, 1;
+    %delay 50, 0;
+    %vpi_call 2 19 "$finish" {0 0 0};
+    %end;
+    .thread T_3;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "knightRiderTB.v";
+    "knightRider.v";
diff --git a/iverilog/tobb/lab5/knightRider.v b/iverilog/tobb/lab5/knightRider.v
new file mode 100644
index 0000000..6f752c5
--- /dev/null
+++ b/iverilog/tobb/lab5/knightRider.v
@@ -0,0 +1,31 @@
+module knightRider (
+    input clk,
+    output reg [7:0] leds
+);
+
+reg direction;
+
+initial begin
+    leds = 8'b0000_0111;
+    direction = 1'b0; // 0 left to right
+end
+
+always@(posedge clk) begin
+if (direction == 0) begin
+    if (leds == 8'b1110_0000) begin
+        direction <= 1;
+        leds <= leds >> 1;
+    end else begin
+        leds <= leds << 1;
+    end
+end else begin
+        if (leds == 8'b0000_0111) begin
+            direction <= 0;
+            leds <= leds << 1;
+        end else begin
+            leds <= leds >> 1;
+        end
+    end
+end
+
+endmodule
diff --git a/iverilog/tobb/lab5/knightRider.vcd b/iverilog/tobb/lab5/knightRider.vcd
new file mode 100644
index 0000000..02025f2
--- /dev/null
+++ b/iverilog/tobb/lab5/knightRider.vcd
@@ -0,0 +1,104 @@
+$date
+	Sat Jan 25 05:37:22 2025
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module knightRiderTB $end
+$var wire 8 ! leds [7:0] $end
+$var reg 1 " clk $end
+$scope module uut $end
+$var wire 1 " clk $end
+$var reg 1 # direction $end
+$var reg 8 $ leds [7:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+b111 $
+0#
+0"
+b111 !
+$end
+#2
+b1110 !
+b1110 $
+1"
+#4
+0"
+#6
+b11100 !
+b11100 $
+1"
+#8
+0"
+#10
+b111000 !
+b111000 $
+1"
+#12
+0"
+#14
+b1110000 !
+b1110000 $
+1"
+#16
+0"
+#18
+b11100000 !
+b11100000 $
+1"
+#20
+0"
+#22
+b1110000 !
+b1110000 $
+1#
+1"
+#24
+0"
+#26
+b111000 !
+b111000 $
+1"
+#28
+0"
+#30
+b11100 !
+b11100 $
+1"
+#32
+0"
+#34
+b1110 !
+b1110 $
+1"
+#36
+0"
+#38
+b111 !
+b111 $
+1"
+#40
+0"
+#42
+b1110 !
+b1110 $
+0#
+1"
+#44
+0"
+#46
+b11100 !
+b11100 $
+1"
+#48
+0"
+#50
+b111000 !
+b111000 $
+1"
diff --git a/iverilog/tobb/lab5/knightRiderTB.v b/iverilog/tobb/lab5/knightRiderTB.v
new file mode 100644
index 0000000..fbf0e9f
--- /dev/null
+++ b/iverilog/tobb/lab5/knightRiderTB.v
@@ -0,0 +1,22 @@
+module knightRiderTB();
+
+reg clk;
+wire [7:0] leds;
+
+knightRider uut (
+    .clk(clk),
+    .leds(leds)
+);
+
+always begin
+    clk = ~clk; #2;
+end
+
+initial begin
+    $dumpfile("knightRider.vcd");
+    $dumpvars;
+    clk = 0; #50;
+    $finish;
+end
+
+endmodule