some random things

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2025-01-08 01:05:46 +03:00
parent ceede4abc3
commit 39d8168cc0
11 changed files with 1474 additions and 13 deletions

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project0.2/PU.v Normal file
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module PU (
input A, // Dividend bit
input B, // Divisor bit
input Cin, // Carry input
input S, // Select input for the mux
output Y, // Output of the PU
output COut // Carry output from the full adder
);
wire Sum, notB;
// Invert B for subtraction
not n1 (notB, B);
// Full adder performs A - B + Cin
fulladder f1 (
.A(A),
.B(notB),
.Carry(Cin),
.Sum(Sum),
.CarryO(COut)
);
// 2:1 multiplexer to select between A and Sum
mux2 m1 (
.A0(A), // Input 0 of mux
.A1(Sum), // Input 1 of mux
.S(S), // Select line
.Y(Y) // Output of the mux
);
endmodule