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verilog

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This commit is contained in:
k0rrluna 2024-07-07 15:51:02 +03:00
parent c1f0851a45
commit 339ae1f428
35 changed files with 26577 additions and 1 deletions
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2
gowin/fpga_project/impl/fpga_project_process_config.json
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@ -18,7 +18,7 @@
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
"Enable_DSRM" : false,
"FORMAT" : "binary",
"FREQUENCY_DIVIDER" : "",
"FREQUENCY_DIVIDER" : "1",
"Generate_Constraint_File_of_Ports" : false,
"Generate_IBIS_File" : false,
"Generate_Plain_Text_Timing_Report" : false,

25
gowin/seq_light_test/impl/gwsynthesis/seq_light_test.log Normal file
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@ -0,0 +1,25 @@
GowinSynthesis start
Running parser ...
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seqBlink.v'
Compiling module 'seqBlink'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seqBlink.v":1)
WARN (EX3791) : Expression size 4 truncated to fit in target size 3("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seqBlink.v":23)
NOTE (EX0101) : Current top module is "seqBlink"
[5%] Running netlist conversion ...
Running device independent optimization ...
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
[95%] Generate netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg" completed
[100%] Generate report file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test_syn.rpt.html" completed
GowinSynthesis finish

19
gowin/seq_light_test/impl/gwsynthesis/seq_light_test.prj Normal file
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@ -0,0 +1,19 @@
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
<Version>beta</Version>
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
<FileList>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seqBlink.v" type="verilog"/>
</FileList>
<OptionList>
<Option type="disable_insert_pad" value="0"/>
<Option type="global_freq" value="100.000"/>
<Option type="looplimit" value="2000"/>
<Option type="output_file" value="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg"/>
<Option type="print_all_synthesis_warning" value="0"/>
<Option type="ram_rw_check" value="0"/>
<Option type="verilog_language" value="verilog-2001"/>
<Option type="vhdl_language" value="vhdl-1993"/>
</OptionList>
</Project>

275
gowin/seq_light_test/impl/gwsynthesis/seq_light_test.vg Normal file
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@ -0,0 +1,275 @@
//
//Written by GowinSynthesis
//Tool Version "V1.9.9.03 Education (64-bit)"
//Sun Jul 7 15:45:04 2024
//Source file index table:
//file0 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/src/seqBlink.v"
`pragma protect begin_protected
`pragma protect version="2.3"
`pragma protect author="default"
`pragma protect author_info="default"
`pragma protect encrypt_agent="GOWIN"
`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
`pragma protect key_block
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`pragma protect encoding=(enctype="base64", line_length=76, bytes=13968)
`pragma protect data_keyowner="default-ip-vendor"
`pragma protect data_keyname="default-ip-key"
`pragma protect data_method="aes128-cfb"
`pragma protect data_block
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`pragma protect end_protected

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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Hierarchy Module Resource</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
div#main_wrapper{ width: 100%; }
h1 {text-align: center; }
h1 {margin-top: 36px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { align = "center"; padding: 5px 2px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="content">
<h1>Hierarchy Module Resource</h1>
<table>
<tr>
<th class="label">MODULE NAME</th>
<th class="label">REG NUMBER</th>
<th class="label">ALU NUMBER</th>
<th class="label">LUT NUMBER</th>
<th class="label">DSP NUMBER</th>
<th class="label">BSRAM NUMBER</th>
<th class="label">SSRAM NUMBER</th>
<th class="label">ROM16 NUMBER</th>
</tr>
<tr>
<td class="label">seqBlink (//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/src/seqBlink.v)</td>
<td align = "center">40</td>
<td align = "center">31</td>
<td align = "center">23</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<Module name="seqBlink" Register="40" Alu="31" Lut="23" T_Register="40(40)" T_Alu="31(31)" T_Lut="23(23)"/>

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-d \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg
-p GW2A-18C-PBGA256-8
-pn GW2A-LV18PG256C8/I7
-cst \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seq_light_test.cst
-cfg \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\device.cfg
-bit
-tr
-ph
-timing
-cst_error
-correct_hold 1
-route_maxfan 23
-global_freq 100.000

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set JTAG regular_io = false
set SSPI regular_io = false
set MSPI regular_io = false
set READY regular_io = false
set DONE regular_io = false
set I2C regular_io = false
set RECONFIG_N regular_io = false
set CRC_check = true
set compress = false
set encryption = false
set security_bit_enable = true
set bsram_init_fuse_print = true
set background_programming = off
set secure_mode = false
set program_done_bypass = false
set wake_up = 0
set format = binary
set power_on_reset_monitor = true
set multiboot_spi_flash_address = 0x00000000
set vccx = 3.3
set unused_pin = default

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Reading netlist file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg"
Parsing netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg" completed
Processing netlist completed
Reading constraint file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seq_light_test.cst"
Physical Constraint parsed completed
Running placement......
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
[30%] Placement Phase 2 completed
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.power.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.pin.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.rpt.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.rpt.txt" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.tr.html" completed
Sun Jul 7 15:45:27 2024

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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//ENhttp://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Power Analysis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper { width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td {white-space:pre; border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.thermal_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.Configure_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table th.label { min-width: 8%; width: 8%; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#Message" style=" font-size: 16px;">Power Messages</a>
<ul>
<li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li>
</ul>
</li>
<li><a href="#Summary" style=" font-size: 16px;">Power Summary</a>
<ul>
<li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li>
<li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li>
<li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li>
</ul>
</li>
<li><a href="#Detail" style=" font-size: 16px;">Power Details</a>
<ul>
<li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li>
<li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li>
<li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="Message">Power Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Power Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seq_light_test.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.9.03 Education (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sun Jul 7 15:45:13 2024
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h2><a name="Configure_Info">Configure Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Grade</td>
<td>Commercial</td>
</tr>
<tr>
<td class="label">Process</td>
<td>Typical</td>
</tr>
<tr>
<td class="label">Ambient Temperature</td>
<td>25.000
</tr>
<tr>
<td class="label">Use Custom Theta JA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Heat Sink</td>
<td>None</td>
</tr>
<tr>
<td class="label">Air Flow</td>
<td>LFM_0</td>
</tr>
<tr>
<td class="label">Use Custom Theta SA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Board Thermal Model</td>
<td>None</td>
</tr>
<tr>
<td class="label">Use Custom Theta JB</td>
<td>false</td>
</tr>
<tr>
<td class="label">Related Vcd File</td>
<td></td>
</tr>
<tr>
<td class="label">Related Saif File</td>
<td></td>
</tr>
<tr>
<td class="label">Filter Glitches</td>
<td>false</td>
</tr>
<tr>
<td class="label">Default IO Toggle Rate</td>
<td>0.125</td>
</tr>
<tr>
<td class="label">Default Remain Toggle Rate</td>
<td>0.125</td>
</tr>
</table>
<h1><a name="Summary">Power Summary</a></h1>
<h2><a name="Power_Info">Power Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Total Power (mW)</td>
<td>124.846</td>
</tr>
<tr>
<td class="label">Quiescent Power (mW)</td>
<td>121.198</td>
</tr>
<tr>
<td class="label">Dynamic Power (mW)</td>
<td>3.647</td>
</tr>
</table>
<h2><a name="Thermal_Info">Thermal Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Junction Temperature</td>
<td>28.998</td>
</tr>
<tr>
<td class="label">Theta JA</td>
<td>32.020</td>
</tr>
<tr>
<td class="label">Max Allowed Ambient Temperature</td>
<td>81.002</td>
</tr>
</table>
<h2><a name="Supply_Summary">Supply Information:</a></h2>
<table class="summary_table">
<tr>
<th class="label">Voltage Source</th>
<th class="label">Voltage</th>
<th class="label">Dynamic Current(mA)</th>
<th class="label">Quiescent Current(mA)</th>
<th class="label">Power(mW)</th>
</tr>
<tr>
<td>VCC</td>
<td>1.000</td>
<td>0.863</td>
<td>69.994</td>
<td>70.857</td>
</tr>
<tr>
<td>VCCX</td>
<td>3.300</td>
<td>0.548</td>
<td>15.000</td>
<td>51.307</td>
</tr>
<tr>
<td>VCCIO18</td>
<td>1.800</td>
<td>0.543</td>
<td>0.947</td>
<td>2.682</td>
</tr>
</table>
<h1><a name="Detail">Power Details</a></h1>
<h2><a name="By_Block_Type">Power By Block Type:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Block Type</th>
<th class="label">Total Power(mW)</th>
<th class="label">Static Power(mW)</th>
<th class="label">Average Toggle Rate(millions of transitions/sec)</th>
</tr>
<tr>
<td>Logic</td>
<td>0.288</td>
<td>NA</td>
<td>13.206</td>
</tr>
<tr>
<td>IO</td>
<td>5.886
<td>2.553
<td>30.000
</tr>
</table>
<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Hierarchy Entity</th>
<th class="label">Total Power(mW)</th>
<th class="label">Block Dynamic Power(mW)</th>
</tr>
<tr>
<td>seqBlink</td>
<td>0.288</td>
<td>0.288(0.000)</td>
</table>
<h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Domain</th>
<th class="label">Clock Frequency(Mhz)</th>
<th class="label">Total Dynamic Power(mW)</th>
</tr>
<tr>
<td>newclk</td>
<td>100.000</td>
<td>0.024</td>
</tr>
<tr>
<td>clock</td>
<td>100.000</td>
<td>0.291</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

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//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
1. PnR Messages
<Report Title>: PnR Report
<Design File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg
<Physical Constraints File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seq_light_test.cst
<Timing Constraints File>: ---
<Tool Version>: V1.9.9.03 Education (64-bit)
<Part Number>: GW2A-LV18PG256C8/I7
<Device>: GW2A-18
<Device Version>: C
<Created Time>:Sun Jul 7 15:45:18 2024
2. PnR Details
Running placement:
Placement Phase 0: CPU time = 0h 0m 0.01s, Elapsed time = 0h 0m 0.01s
Placement Phase 1: CPU time = 0h 0m 0.529s, Elapsed time = 0h 0m 0.529s
Placement Phase 2: CPU time = 0h 0m 0.012s, Elapsed time = 0h 0m 0.012s
Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Running routing:
Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Routing Phase 1: CPU time = 0h 0m 0.254s, Elapsed time = 0h 0m 0.254s
Routing Phase 2: CPU time = 0h 0m 0.283s, Elapsed time = 0h 0m 0.283s
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Total Routing: CPU time = 0h 0m 0.537s, Elapsed time = 0h 0m 0.537s
Generate output files:
CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s
Total Time and Memory Usage: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 439MB
3. Resource Usage Summary
----------------------------------------------------------
Resources | Usage
----------------------------------------------------------
Logic | 55/20736 <1%
--LUT,ALU,ROM16 | 55(23 LUT, 32 ALU, 0 ROM16)
--SSRAM(RAM16) | 0
Register | 40/16173 <1%
--Logic Register as Latch | 0/15552 0%
--Logic Register as FF | 36/15552 <1%
--I/O Register as Latch | 0/621 0%
--I/O Register as FF | 4/621 <1%
CLS | 30/10368 <1%
I/O Port | 5
I/O Buf | 5
--Input Buf | 1
--Output Buf | 4
--Inout Buf | 0
IOLOGIC | 0%
BSRAM | 0%
DSP | 0%
PLL | 0/4 0%
DCS | 0/8 0%
DQCE | 0/24 0%
OSC | 0/1 0%
CLKDIV | 0/8 0%
DLLDLY | 0/8 0%
DQS | 0/9 0%
DHCEN | 0/16 0%
==========================================================
4. I/O Bank Usage Summary
-----------------------
I/O Bank | Usage
-----------------------
bank 0 | 1/29(3%)
bank 1 | 4/20(20%)
bank 2 | 0/20(0%)
bank 3 | 0/32(0%)
bank 4 | 0/36(0%)
bank 5 | 0/36(0%)
bank 6 | 0/18(0%)
bank 7 | 0/16(0%)
=======================
5. Global Clock Usage Summary
-------------------------------
Global Clock | Usage
-------------------------------
PRIMARY | 2/8(25%)
LW | 0/8(0%)
GCLK_PIN | 1/8(13%)
PLL | 0/4(0%)
CLKDIV | 0/8(0%)
DLLDLY | 0/8(0%)
===============================
6. Global Clock Signals
-------------------------------------------
Signal | Global Clock | Location
-------------------------------------------
clock_d | PRIMARY | TR TL BL
newclk | PRIMARY | TR BL
===========================================
7. Pinout by Port Name
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | BankVccio
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
clock | | H11/0 | Y | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
led[0] | | N16/1 | Y | out | IOT52[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
led[1] | | N14/1 | Y | out | IOT52[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
led[2] | | L14/1 | Y | out | IOT34[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
led[3] | | L16/1 | Y | out | IOT34[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
==================================================================================================================================================================================================================
8. All Package Pins
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Loc./Bank| Signal | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | Bank Vccio
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
L15/0 | - | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D16/0 | - | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E14/0 | - | in | IOT4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C16/0 | - | in | IOT5[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D15/0 | - | in | IOT5[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E16/0 | - | in | IOT6[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F15/0 | - | in | IOT6[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F13/0 | - | in | IOT8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G12/0 | - | in | IOT8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F14/0 | - | in | IOT9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F16/0 | - | in | IOT9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F12/0 | - | in | IOT12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G13/0 | - | in | IOT12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G15/0 | - | in | IOT13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G14/0 | - | in | IOT13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G11/0 | - | in | IOT14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H12/0 | - | in | IOT14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G16/0 | - | in | IOT16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H15/0 | - | in | IOT16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H13/0 | - | in | IOT18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J12/0 | - | in | IOT18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H14/0 | - | in | IOT20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H16/0 | - | in | IOT20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J16/0 | - | in | IOT22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J14/0 | - | in | IOT22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J15/0 | - | in | IOT24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K16/0 | - | in | IOT24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H11/0 | clock | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J13/0 | - | in | IOT27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K14/1 | - | in | IOT30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K15/1 | - | in | IOT30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J11/1 | - | in | IOT32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L12/1 | - | in | IOT32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L16/1 | led[3] | out | IOT34[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
L14/1 | led[2] | out | IOT34[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
K13/1 | - | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K12/1 | - | in | IOT36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K11/1 | - | in | IOT38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L13/1 | - | in | IOT38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M14/1 | - | in | IOT40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M15/1 | - | in | IOT40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D14/1 | - | in | IOT44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E15/1 | - | in | IOT44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N15/1 | - | in | IOT48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P16/1 | - | in | IOT48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N16/1 | led[0] | out | IOT52[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
N14/1 | led[1] | out | IOT52[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
P15/1 | - | in | IOT54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R16/1 | - | in | IOT54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
A4/5 | - | in | IOB2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C5/5 | - | in | IOB2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D6/5 | - | in | IOB3[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E7/5 | - | in | IOB3[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A3/5 | - | in | IOB4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B4/5 | - | in | IOB4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A5/5 | - | in | IOB7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B6/5 | - | in | IOB7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B1/5 | - | in | IOB8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C2/5 | - | in | IOB8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D3/5 | - | in | IOB9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D1/5 | - | in | IOB9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E2/5 | - | in | IOB12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E3/5 | - | in | IOB12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B3/5 | - | in | IOB13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A2/5 | - | in | IOB13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C1/5 | - | in | IOB14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D2/5 | - | in | IOB14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E1/5 | - | in | IOB16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F2/5 | - | in | IOB16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F4/5 | - | in | IOB18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G6/5 | - | in | IOB18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F3/5 | - | in | IOB19[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F1/5 | - | in | IOB19[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G5/5 | - | in | IOB20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G4/5 | - | in | IOB20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G2/5 | - | in | IOB21[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G3/5 | - | in | IOB21[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F5/5 | - | in | IOB22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H6/5 | - | in | IOB22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G1/5 | - | in | IOB24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H2/5 | - | in | IOB24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H4/5 | - | in | IOB26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J6/5 | - | in | IOB26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J1/5 | - | in | IOB27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J3/5 | - | in | IOB27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L2/4 | - | in | IOB30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M1/4 | - | in | IOB30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H3/4 | - | in | IOB32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H1/4 | - | in | IOB32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J2/4 | - | in | IOB34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K1/4 | - | in | IOB34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H5/4 | - | in | IOB35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J4/4 | - | in | IOB35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K3/4 | - | in | IOB36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K2/4 | - | in | IOB36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J5/4 | - | in | IOB37[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K6/4 | - | in | IOB37[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L1/4 | - | in | IOB38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L3/4 | - | in | IOB38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K4/4 | - | in | IOB39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L5/4 | - | in | IOB39[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K5/4 | - | in | IOB40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L4/4 | - | in | IOB40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N2/4 | - | in | IOB41[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P1/4 | - | in | IOB41[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M3/4 | - | in | IOB42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N1/4 | - | in | IOB42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M2/4 | - | in | IOB43[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N3/4 | - | in | IOB43[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R1/4 | - | in | IOB44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P2/4 | - | in | IOB44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P4/4 | - | in | IOB45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T4/4 | - | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R3/4 | - | in | IOB48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T2/4 | - | in | IOB48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P5/4 | - | in | IOB50[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R5/4 | - | in | IOB50[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R4/4 | - | in | IOB52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T3/4 | - | in | IOB52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R6/4 | - | in | IOB54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T5/4 | - | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
B14/7 | - | in | IOL2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A15/7 | - | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C12/7 | - | in | IOL7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B12/7 | - | in | IOL7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B13/7 | - | in | IOL8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A14/7 | - | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F10/7 | - | in | IOL11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B11/7 | - | in | IOL13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A12/7 | - | in | IOL13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A11/7 | - | in | IOL15[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C11/7 | - | in | IOL15[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D10/7 | - | in | IOL17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E10/7 | - | in | IOL17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D11/7 | - | in | IOL22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A9/7 | - | in | IOL27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C9/7 | - | in | IOL27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C8/6 | - | in | IOL29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A8/6 | - | in | IOL29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F9/6 | - | in | IOL31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E11/6 | - | in | IOL31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B9/6 | - | in | IOL33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A10/6 | - | in | IOL33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F8/6 | - | in | IOL35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D9/6 | - | in | IOL35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D8/6 | - | in | IOL38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E9/6 | - | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B7/6 | - | in | IOL40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C7/6 | - | in | IOL40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F7/6 | - | in | IOL45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E8/6 | - | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C4/6 | - | in | IOL47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B5/6 | - | in | IOL47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E6/6 | - | in | IOL53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D7/6 | - | in | IOL53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
T15/2 | - | in | IOR7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R14/2 | - | in | IOR7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P12/2 | - | in | IOR8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T13/2 | - | in | IOR8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R12/2 | - | in | IOR11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P13/2 | - | in | IOR11[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R11/2 | - | in | IOR17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T12/2 | - | in | IOR17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R13/2 | - | in | IOR20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T14/2 | - | in | IOR20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M10/2 | - | in | IOR22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N11/2 | - | in | IOR22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T11/2 | - | in | IOR24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P11/2 | - | in | IOR24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C6/2 | - | out | IOR25[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
B8/2 | - | in | IOR25[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A7/2 | - | in | IOR26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A6/2 | - | in | IOR26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N10/2 | - | in | IOR27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M11/2 | - | in | IOR27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T7/3 | - | in | IOR29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R8/3 | - | in | IOR29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M16/3 | - | in | IOR30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B16/3 | - | in | IOR30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C15/3 | - | in | IOR31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B10/3 | - | in | IOR31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A13/3 | - | in | IOR32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C13/3 | - | in | IOR32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P10/3 | - | in | IOR33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R10/3 | - | in | IOR33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M9/3 | - | in | IOR34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L10/3 | - | in | IOR34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R9/3 | - | in | IOR35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T10/3 | - | in | IOR35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M8/3 | - | in | IOR36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N9/3 | - | in | IOR36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T9/3 | - | in | IOR38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P9/3 | - | in | IOR38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C10/3 | - | in | IOR39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N8/3 | - | in | IOR40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L9/3 | - | in | IOR40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P8/3 | - | in | IOR42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T8/3 | - | in | IOR42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M6/3 | - | in | IOR44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L8/3 | - | in | IOR44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M7/3 | - | in | IOR47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N7/3 | - | in | IOR47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R7/3 | - | in | IOR49[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P7/3 | - | in | IOR49[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N6/3 | - | in | IOR51[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P6/3 | - | in | IOR53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T6/3 | - | in | IOR53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
====================================================================================================================================================================================

941
gowin/seq_light_test/impl/pnr/seq_light_test.timing_paths Normal file
View File

@ -0,0 +1,941 @@
=====
SETUP
6.732
9.734
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_24_s0
9.734
=====
SETUP
6.732
9.734
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_25_s0
9.734
=====
SETUP
6.732
9.734
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_26_s0
9.734
=====
SETUP
6.732
9.734
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_27_s0
9.734
=====
SETUP
6.732
9.734
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_28_s0
9.734
=====
SETUP
6.732
9.734
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_29_s0
9.734
=====
SETUP
6.740
9.726
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_31_s0
9.726
=====
SETUP
6.740
9.726
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_30_s0
9.726
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_12_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_13_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_14_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_15_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_16_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_17_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_18_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_19_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_20_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_21_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_22_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_23_s0
9.543
=====
SETUP
6.927
9.539
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_1_s0
9.539
=====
SETUP
6.927
9.539
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_2_s0
9.539
=====
SETUP
6.927
9.539
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_3_s0
9.539
=====
SETUP
6.927
9.539
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_4_s0
9.539
=====
SETUP
6.927
9.539
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_5_s0
9.539
=====
HOLD
-4.449
0.234
4.684
n72_s2
0.002
0.234
newclk_s1
0.234
=====
HOLD
0.425
5.074
4.649
clock_ibuf
0.000
3.126
clkcnt_2_s0
4.638
4.840
n35_s
4.842
5.074
clkcnt_2_s0
5.074
=====
HOLD
0.425
5.074
4.649
clock_ibuf
0.000
3.126
clkcnt_6_s0
4.638
4.840
n31_s
4.842
5.074
clkcnt_6_s0
5.074
=====
HOLD
0.425
5.074
4.649
clock_ibuf
0.000
3.126
clkcnt_8_s0
4.638
4.840
n29_s
4.842
5.074
clkcnt_8_s0
5.074
=====
HOLD
0.425
5.074
4.649
clock_ibuf
0.000
3.126
clkcnt_14_s0
4.638
4.840
n23_s
4.842
5.074
clkcnt_14_s0
5.074
=====
HOLD
0.425
5.074
4.649
clock_ibuf
0.000
3.126
clkcnt_20_s0
4.638
4.840
n17_s
4.842
5.074
clkcnt_20_s0
5.074
=====
HOLD
0.425
5.074
4.649
clock_ibuf
0.000
3.126
clkcnt_24_s0
4.638
4.840
n13_s
4.842
5.074
clkcnt_24_s0
5.074
=====
HOLD
0.425
5.074
4.649
clock_ibuf
0.000
3.126
clkcnt_26_s0
4.638
4.840
n11_s
4.842
5.074
clkcnt_26_s0
5.074
=====
HOLD
0.425
5.074
4.649
clock_ibuf
0.000
3.126
clkcnt_30_s0
4.638
4.840
n7_s
4.842
5.074
clkcnt_30_s0
5.074
=====
HOLD
0.425
2.197
1.771
fsm_2_s0
1.760
1.962
n111_s0
1.965
2.197
fsm_2_s0
2.197
=====
HOLD
0.427
5.075
4.649
clock_ibuf
0.000
3.126
clkcnt_0_s0
4.638
4.840
n37_s2
4.843
5.075
clkcnt_0_s0
5.075
=====
HOLD
0.427
5.075
4.649
clock_ibuf
0.000
3.126
clkcnt_12_s0
4.638
4.840
n25_s
4.843
5.075
clkcnt_12_s0
5.075
=====
HOLD
0.427
5.075
4.649
clock_ibuf
0.000
3.126
clkcnt_18_s0
4.638
4.840
n19_s
4.843
5.075
clkcnt_18_s0
5.075
=====
HOLD
0.542
5.191
4.649
clock_ibuf
0.000
3.126
clkcnt_31_s0
4.638
4.839
n6_s
4.959
5.191
clkcnt_31_s0
5.191
=====
HOLD
0.542
5.191
4.649
clock_ibuf
0.000
3.126
clkcnt_11_s0
4.638
4.839
n26_s
4.959
5.191
clkcnt_11_s0
5.191
=====
HOLD
0.542
5.191
4.649
clock_ibuf
0.000
3.126
clkcnt_23_s0
4.638
4.839
n14_s
4.959
5.191
clkcnt_23_s0
5.191
=====
HOLD
0.546
5.194
4.649
clock_ibuf
0.000
3.126
clkcnt_3_s0
4.638
4.839
n34_s
4.962
5.194
clkcnt_3_s0
5.194
=====
HOLD
0.546
5.194
4.649
clock_ibuf
0.000
3.126
clkcnt_4_s0
4.638
4.839
n33_s
4.962
5.194
clkcnt_4_s0
5.194
=====
HOLD
0.546
5.194
4.649
clock_ibuf
0.000
3.126
clkcnt_9_s0
4.638
4.839
n28_s
4.962
5.194
clkcnt_9_s0
5.194
=====
HOLD
0.546
5.194
4.649
clock_ibuf
0.000
3.126
clkcnt_16_s0
4.638
4.839
n21_s
4.962
5.194
clkcnt_16_s0
5.194
=====
HOLD
0.546
5.194
4.649
clock_ibuf
0.000
3.126
clkcnt_21_s0
4.638
4.839
n16_s
4.962
5.194
clkcnt_21_s0
5.194
=====
HOLD
0.546
5.194
4.649
clock_ibuf
0.000
3.126
clkcnt_22_s0
4.638
4.839
n15_s
4.962
5.194
clkcnt_22_s0
5.194
=====
HOLD
0.546
5.194
4.649
clock_ibuf
0.000
3.126
clkcnt_27_s0
4.638
4.839
n10_s
4.962
5.194
clkcnt_27_s0
5.194
=====
HOLD
0.546
5.194
4.649
clock_ibuf
0.000
3.126
clkcnt_28_s0
4.638
4.839
n9_s
4.962
5.194
clkcnt_28_s0
5.194
=====
HOLD
0.546
5.194
4.649
clock_ibuf
0.000
3.126
clkcnt_29_s0
4.638
4.839
n8_s
4.962
5.194
clkcnt_29_s0
5.194

10
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</html>

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gowin/seq_light_test/impl/pnr/seq_light_test_tr_content.html Normal file
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File diff suppressed because it is too large Load Diff

88
gowin/seq_light_test/impl/seq_light_test_process_config.json Normal file
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@ -0,0 +1,88 @@
{
"BACKGROUND_PROGRAMMING" : "off",
"COMPRESS" : false,
"CPU" : false,
"CRC_CHECK" : true,
"Clock_Route_Order" : 0,
"Correct_Hold_Violation" : true,
"DONE" : false,
"DOWNLOAD_SPEED" : "default",
"Disable_Insert_Pad" : false,
"ENABLE_CTP" : false,
"ENABLE_MERGE_MODE" : false,
"ENCRYPTION_KEY" : false,
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
"ERROR_DECTION_AND_CORRECTION" : false,
"ERROR_DECTION_ONLY" : false,
"ERROR_INJECTION" : false,
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
"Enable_DSRM" : false,
"FORMAT" : "binary",
"FREQUENCY_DIVIDER" : "",
"Generate_Constraint_File_of_Ports" : false,
"Generate_IBIS_File" : false,
"Generate_Plain_Text_Timing_Report" : false,
"Generate_Post_PNR_Simulation_Model_File" : false,
"Generate_Post_Place_File" : false,
"Generate_SDF_File" : false,
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
"Global_Freq" : "default",
"GwSyn_Loop_Limit" : 2000,
"HOTBOOT" : false,
"I2C" : false,
"I2C_SLAVE_ADDR" : "00",
"IncludePath" : [
],
"Incremental_Compile" : "",
"Initialize_Primitives" : false,
"JTAG" : false,
"MODE_IO" : false,
"MSPI" : false,
"MSPI_JUMP" : false,
"MULTIBOOT_ADDRESS_WIDTH" : "24",
"MULTIBOOT_MODE" : "Normal",
"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
"MULTIJUMP_ADDRESS_WIDTH" : "24",
"MULTIJUMP_MODE" : "Normal",
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
"Multi_Boot" : true,
"OUTPUT_BASE_NAME" : "seq_light_test",
"POWER_ON_RESET_MONITOR" : true,
"PRINT_BSRAM_VALUE" : true,
"PROGRAM_DONE_BYPASS" : false,
"PlaceInRegToIob" : true,
"PlaceIoRegToIob" : true,
"PlaceOutRegToIob" : true,
"Place_Option" : "0",
"Process_Configuration_Verion" : "1.0",
"Promote_Physical_Constraint_Warning_to_Error" : true,
"READY" : false,
"RECONFIG_N" : false,
"Ram_RW_Check" : false,
"Replicate_Resources" : false,
"Report_Auto-Placed_Io_Information" : false,
"Route_Maxfan" : 23,
"Route_Option" : "0",
"Run_Timing_Driven" : true,
"SECURE_MODE" : false,
"SECURITY_BIT" : true,
"SEU_HANDLER" : false,
"SEU_HANDLER_CHECKSUM" : false,
"SEU_HANDLER_MODE" : "auto",
"SSPI" : false,
"STOP_SEU_HANDLER" : false,
"Show_All_Warnings" : false,
"Synthesize_tool" : "GowinSyn",
"TclPre" : "",
"TopModule" : "",
"USERCODE" : "default",
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
"VCCAUX" : 3.3,
"VCCX" : "3.3",
"VHDL_Standard" : "VHDL_Std_1993",
"Verilog_Standard" : "Vlg_Std_2001",
"WAKE_UP" : "0",
"show_all_warnings" : false,
"turn_off_bg" : false
}

10
gowin/seq_light_test/impl/temp/rtl_parser.result Normal file
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[
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/src/seqBlink.v",
"InstLine" : 1,
"InstName" : "seqBlink",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/src/seqBlink.v",
"ModuleLine" : 1,
"ModuleName" : "seqBlink"
}
]

17
gowin/seq_light_test/impl/temp/rtl_parser_arg.json Normal file
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{
"Device" : "GW2A-18C",
"Files" : [
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/src/seqBlink.v",
"Type" : "verilog"
}
],
"IncludePath" : [
],
"LoopLimit" : 2000,
"ResultFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/impl/temp/rtl_parser.result",
"Top" : "",
"VerilogStd" : "verilog_2001",
"VhdlStd" : "vhdl_93"
}

0
gowin/seq_light_test/impl/temp/style.css Normal file
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12
gowin/seq_light_test/seq_light_test.gprj Normal file
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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
<FileList>
<File path="src/seqBlink.v" type="file.verilog" enable="1"/>
<File path="src/seqBlinkTB.v" type="file.verilog" enable="0"/>
<File path="src/seq_light_test.cst" type="file.cst" enable="1"/>
</FileList>
</Project>

24
gowin/seq_light_test/seq_light_test.gprj.user Normal file
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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE ProjectUserData>
<UserConfig>
<Version>1.0</Version>
<FlowState>
<Process ID="Synthesis" State="2"/>
<Process ID="Pnr" State="2"/>
<Process ID="Gao" State="2"/>
<Process ID="Rtl_Gao" State="2"/>
</FlowState>
<ResultFileList>
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/seq_light_test.vg"/>
<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/seq_light_test.fs"/>
<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/seq_light_test.pin.html"/>
<ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/seq_light_test.db"/>
<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/seq_light_test.power.html"/>
<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/seq_light_test.rpt.html"/>
<ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/seq_light_test.timing_paths"/>
<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/seq_light_test.tr.html"/>
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/seq_light_test_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/seq_light_test_syn_rsc.xml"/>
</ResultFileList>
<Ui>000000ff00000001fd00000002000000000000018e00000260fc0200000001fc00000063000002600000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000078000000142fc0100000001fc00000000000007800000009b00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000007800fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000009b00ffffff000005ea0000026000000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000afffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000183ffffffff0000000000000000</Ui>
</UserConfig>

36
gowin/seq_light_test/src/seqBlink.v Normal file
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module seqBlink (
input clock,
output reg [3:0] led
);
reg [2:0] fsm = 0;
reg [31:0] clkcnt = 0;
reg newclk = 0;
always@(posedge clock) begin
clkcnt <= clkcnt + 1'b1;
if (clkcnt > 9_000_000) begin
clkcnt <= 0;
newclk <= ~newclk;
end
end
always@(posedge newclk) begin
if (fsm == 3'd6) begin
fsm <= 0;
end else begin
fsm <= fsm + 1;
end
case (fsm)
3'b000 : led <= 4'b0111;
3'b001 : led <= 4'b1011;
3'b010 : led <= 4'b1101;
3'b011 : led <= 4'b1110;
3'b100 : led <= 4'b1101;
3'b101 : led <= 4'b1011;
3'b110 : led <= 4'b0111;
default: led <= 4'b0000;
endcase
end
endmodule

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gowin/seq_light_test/src/seqBlinkTB.v Normal file
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module seqBlinkTB();
reg clock;
wire [3:0] leds;
seqBlink uut(clock, leds);
initial begin
clock = 0;
end
always begin
clock = ~clock; #5;
end
initial begin
$dumpfile("lab5v.vcd");
$dumpvars;
#100;
$finish;
end
endmodule

19
gowin/seq_light_test/src/seq_light_test.cst Normal file
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//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Physical Constraints file
//Tool Version: V1.9.9.03 Education (64-bit)
//Part Number: GW2A-LV18PG256C8/I7
//Device: GW2A-18
//Device Version: C
//Created Time: Sun 07 07 15:26:30 2024
IO_LOC "led[3]" L16;
IO_PORT "led[3]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "led[2]" L14;
IO_PORT "led[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "led[1]" N14;
IO_PORT "led[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "led[0]" N16;
IO_PORT "led[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "clock" H11;
IO_PORT "clock" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;

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labs/lab5/lab5 Normal file
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#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55ec01128cc0 .scope module, "seqBlinkTB" "seqBlinkTB" 2 1;
.timescale 0 0;
v0x55ec01139850_0 .var "clock", 0 0;
v0x55ec01139920_0 .net "leds", 3 0, v0x55ec01139650_0; 1 drivers
S_0x55ec01128e50 .scope module, "uut" "seqBlink" 2 6, 3 1 0, S_0x55ec01128cc0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clock";
.port_info 1 /OUTPUT 4 "leds";
v0x55ec010f07f0_0 .net "clock", 0 0, v0x55ec01139850_0; 1 drivers
v0x55ec010f0c00_0 .var "count", 1 0;
v0x55ec01139650_0 .var "leds", 3 0;
v0x55ec01139710_0 .var "start", 3 0;
E_0x55ec01127bc0 .event posedge, v0x55ec010f07f0_0;
.scope S_0x55ec01128e50;
T_0 ;
%pushi/vec4 0, 0, 2;
%store/vec4 v0x55ec010f0c00_0, 0, 2;
%pushi/vec4 1, 0, 4;
%store/vec4 v0x55ec01139710_0, 0, 4;
%end;
.thread T_0;
.scope S_0x55ec01128e50;
T_1 ;
%wait E_0x55ec01127bc0;
%load/vec4 v0x55ec010f0c00_0;
%addi 1, 0, 2;
%assign/vec4 v0x55ec010f0c00_0, 0;
%load/vec4 v0x55ec01139710_0;
%ix/getv 4, v0x55ec010f0c00_0;
%shiftl 4;
%assign/vec4 v0x55ec01139650_0, 0;
%jmp T_1;
.thread T_1;
.scope S_0x55ec01128cc0;
T_2 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55ec01139850_0, 0, 1;
T_2.0 ;
%delay 5, 0;
%load/vec4 v0x55ec01139850_0;
%inv;
%store/vec4 v0x55ec01139850_0, 0, 1;
%jmp T_2.0;
%end;
.thread T_2;
.scope S_0x55ec01128cc0;
T_3 ;
%vpi_call 2 16 "$dumpfile", "lab5v.vcd" {0 0 0};
%vpi_call 2 17 "$dumpvars" {0 0 0};
%delay 100, 0;
%vpi_call 2 21 "$finish" {0 0 0};
%end;
.thread T_3;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"seqBlinkTB.v";
"seqBlink.v";

98
labs/lab5/lab5v.vcd Normal file
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$date
Sun Jul 7 02:46:47 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module seqBlinkTB $end
$var wire 4 ! leds [3:0] $end
$var reg 1 " clock $end
$scope module uut $end
$var wire 1 " clock $end
$var reg 2 # count [1:0] $end
$var reg 4 $ leds [3:0] $end
$var reg 4 % start [3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b1 %
bx $
b0 #
0"
bx !
$end
#5
b1 !
b1 $
b1 #
1"
#10
0"
#15
b10 !
b10 $
b10 #
1"
#20
0"
#25
b100 !
b100 $
b11 #
1"
#30
0"
#35
b1000 !
b1000 $
b0 #
1"
#40
0"
#45
b1 !
b1 $
b1 #
1"
#50
0"
#55
b10 !
b10 $
b10 #
1"
#60
0"
#65
b100 !
b100 $
b11 #
1"
#70
0"
#75
b1000 !
b1000 $
b0 #
1"
#80
0"
#85
b1 !
b1 $
b1 #
1"
#90
0"
#95
b10 !
b10 $
b10 #
1"
#100
0"

36
labs/lab5/seqBlink.v Normal file
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module seqBlink (
input clock,
output reg [3:0] led
);
reg [2:0] fsm = 0;
reg [31:0] clkcnt = 0;
reg newclk = 0;
always@(posedge clock) begin
clkcnt <= clkcnt + 1'b1;
if (clkcnt > 9_000_000) begin
clkcnt <= 0;
newclk <= ~newclk;
end
end
always@(posedge newclk) begin
if (fsm == 3'd7) begin
fsm <= 0;
end else begin
fsm <= fsm + 1;
end
case (fsm)
3'b000 : led <= 4'b0111;
3'b001 : led <= 4'b1011;
3'b010 : led <= 4'b1101;
3'b011 : led <= 4'b1110;
3'b100 : led <= 4'b1101;
3'b101 : led <= 4'b1011;
3'b110 : led <= 4'b0111;
default: led <= 4'b0000;
endcase
end
endmodule

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labs/lab5/seqBlinkTB.v Normal file
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module seqBlinkTB();
reg clock;
wire [3:0] leds;
seqBlink uut(clock, leds);
initial begin
clock = 0;
forever begin
#5 clock = ~clock;
end
end
initial begin
$dumpfile("lab5v.vcd");
$dumpvars;
#100;
$finish;
end
endmodule