37 lines
710 B
Verilog
37 lines
710 B
Verilog
module seqBlink (
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input clock,
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output reg [3:0] led
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);
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reg [2:0] fsm = 0;
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reg [31:0] clkcnt = 0;
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reg newclk = 0;
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always@(posedge clock) begin
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clkcnt <= clkcnt + 1'b1;
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if (clkcnt > 9_000_000) begin
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clkcnt <= 0;
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newclk <= ~newclk;
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end
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end
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always@(posedge newclk) begin
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if (fsm == 3'd7) begin
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fsm <= 0;
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end else begin
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fsm <= fsm + 1;
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end
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case (fsm)
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3'b000 : led <= 4'b0111;
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3'b001 : led <= 4'b1011;
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3'b010 : led <= 4'b1101;
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3'b011 : led <= 4'b1110;
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3'b100 : led <= 4'b1101;
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3'b101 : led <= 4'b1011;
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3'b110 : led <= 4'b0111;
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default: led <= 4'b0000;
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endcase
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end
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endmodule
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