kaltinsoy/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

verilog

Browse Source
This commit is contained in:
k0rrluna 2024-07-07 15:51:02 +03:00
parent c1f0851a45
commit 339ae1f428
35 changed files with 26577 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
gowin/fpga_project/impl/fpga_project_process_config.json
View File

@ -18,7 +18,7 @@
"EXTERNAL_MASTER_CONFIG_CLOCK" : false, "EXTERNAL_MASTER_CONFIG_CLOCK" : false,
"Enable_DSRM" : false, "Enable_DSRM" : false,
"FORMAT" : "binary", "FORMAT" : "binary",
"FREQUENCY_DIVIDER" : "", "FREQUENCY_DIVIDER" : "1",
"Generate_Constraint_File_of_Ports" : false, "Generate_Constraint_File_of_Ports" : false,
"Generate_IBIS_File" : false, "Generate_IBIS_File" : false,
"Generate_Plain_Text_Timing_Report" : false, "Generate_Plain_Text_Timing_Report" : false,

25
gowin/seq_light_test/impl/gwsynthesis/seq_light_test.log Normal file
View File

@ -0,0 +1,25 @@
GowinSynthesis start
Running parser ...
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seqBlink.v'
Compiling module 'seqBlink'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seqBlink.v":1)
WARN (EX3791) : Expression size 4 truncated to fit in target size 3("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seqBlink.v":23)
NOTE (EX0101) : Current top module is "seqBlink"
[5%] Running netlist conversion ...
Running device independent optimization ...
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
[95%] Generate netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg" completed
[100%] Generate report file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test_syn.rpt.html" completed
GowinSynthesis finish

19
gowin/seq_light_test/impl/gwsynthesis/seq_light_test.prj Normal file
View File

@ -0,0 +1,19 @@
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
<Version>beta</Version>
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
<FileList>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seqBlink.v" type="verilog"/>
</FileList>
<OptionList>
<Option type="disable_insert_pad" value="0"/>
<Option type="global_freq" value="100.000"/>
<Option type="looplimit" value="2000"/>
<Option type="output_file" value="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg"/>
<Option type="print_all_synthesis_warning" value="0"/>
<Option type="ram_rw_check" value="0"/>
<Option type="verilog_language" value="verilog-2001"/>
<Option type="vhdl_language" value="vhdl-1993"/>
</OptionList>
</Project>

275
gowin/seq_light_test/impl/gwsynthesis/seq_light_test.vg Normal file
View File

@ -0,0 +1,275 @@
//
//Written by GowinSynthesis
//Tool Version "V1.9.9.03 Education (64-bit)"
//Sun Jul 7 15:45:04 2024
//Source file index table:
//file0 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/src/seqBlink.v"
`pragma protect begin_protected
`pragma protect version="2.3"
`pragma protect author="default"
`pragma protect author_info="default"
`pragma protect encrypt_agent="GOWIN"
`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
`pragma protect key_block
SZqb9GzeDDOXVjA0NutRW8jYqBdoo16lBDItAmXNB+e3d6MAKZhgJgLdGWP0hwNFRMt6J3s0uPir
cksBdIyPeEarEzHJn7Jbc4THRPCSmyZ0dXs2OciVL+JJ1DnmkI38cmBvtzzqg1sA2eW6Gl8Tf0zH
wIK+FmxD+le5eKeAthEwE4kZP3FJpYe0YFibtcEyyCfvQ8wPS3WvN8583sAde36Ju2Yskguu/2ru
9ZsIOS+amQcO5nUJtCcuclI2OZecxl9cP9b0zcshd+5y3n6NHaFHMsGT5KD0s6Kpupb2KtOheowd
lRaLuMnAD97c6aAa1zrsHdeE3/ODyLMHqH6aJA==
`pragma protect encoding=(enctype="base64", line_length=76, bytes=13968)
`pragma protect data_keyowner="default-ip-vendor"
`pragma protect data_keyname="default-ip-key"
`pragma protect data_method="aes128-cfb"
`pragma protect data_block
nWtjBmqGxvxpLDTYo0uuI3OAab/JOfmlwrLEPXBAa7oRLt1vn1kuTMjvvYX6TTl7DRVQVz+jm/pr
YkgMRPcBcPjzrot/P3F1Cukls78U4vu0kKSII8bt0xzD6zTQMgVl73lnhNPE4c++jWEHjAYjrMuP
NlW+KJbzE5mykzlyCEEtINRjh0UUIZVZxY1AByH0VKdNAkUPW/+7ZnQSCRn2QJfosbp3V85JARH0
pZGQBC5nqjr7CTRfydSrR0mUzOfBPSfROXhMA8/M4q2nHaF2iG54CU2WxwYNyh5Mw9qnxLur3rVY
qZICcTzmGQp+4OnERaUssTTdX6xlUE80wZuxLCQomoLAWV51/PbI9+KlgriVWm4cqx5iXKdD9LYu
k8+zJ9Y298Vo0JFFnydKAszK6DrI4SI82aFHq4R7pgmhrNdf3mbOmaHbVenymkFuAlRSCDtT1ojR
Sf4+sEakVJxRVUZb4VDNSWKXq4I4+DQ3Y/j+BcAW5XRoy3/KTBXn7jwOhGjtpfNSGcxnAd8yjPQS
Hs31zgfQgFLmLT8m9MvCj9CcAQ2nXdKm9bPTHjAsm3cqA5i2Eh3tvw14kp14b3jZIkqcmn6cQZY+
DcZ1R+OaGmchDCAMLo8f82g4q6TphCyxCQwejKXjosyKujNo8G3hCiOekk7T72yKKMzTWgnbvXlw
wm4bvDjCgwXy5/PON84HvQ3lDBLBnES9P0sMIlkS9jCD/WFaCO5/wAcmVR5Lcl52QopU1xCZV7He
OZHqTiJ9RhOqsqxAwyrNr1GMp+ZL+UnlL2GBBefC0erg6JM3AumEN4GtuYRmHOMe0WkrqsE5fcq4
Aw3U6g+v01ZroISjP+omr+PMueEdwlot9vGzvQMIMAA3H0L4VlT+a3GrASgB30Hw0GWZ4fnXeRVS
J7eORcJdu1dg5bCTuFAfoG67JoGrquxhsQoAYV2mIWjyFBTUcWsviCeVhAOjFP35DouReXlmpagl
dCk9kYkOxvyR5rZsu8flxmMkK6AsfX+kV0DibaqTCvR8/DDjpoLhyYNBlsBJRWRtZCZz2ySmlNpL
V3qQbnGoViC2PJvbiJRqE2WWR0GRiTkEngSd/U6kasMxHxPFOP6Psq+2tcEbrktbGfjWGALiMAqI
g27AVAxuGVj521LIIfRkSa5JYgN/4Ohwngzsr+RckNwzRuB8dlmDkVDVvxlLhNEdwkmGPlFCr3oU
h1WqOdlu5zxVAaBT3K/rqxr37BtQ21KQH0SJxYspg+vP+Ktlm0C7CL5rjyveE2N3xY8ytTRxMz/O
EUssPx3I0TMVmltXYqYLnuv5PGMLrAoWj7BnTegx/MBRzj+M7G2xcRhtbdnw9UAwt1cdZr09t+5v
RKFUXMVqVAL/Y/21A5e0kz9QUW+tQ+aIqRt9uQUhrn4Q77EGOR1WuHHbUEIEySY4nOnLesrqL/C0
tCFVJWGYr0mkSLttlUG/db0dixf2nYwu/bQ3asm/QHzppqZ5QFM+P/S4lghlHPgWAVnVJHBSJjyD
JepTU2bEpmrTj8L3FqAHmUt3hVbNp0RIa5XI7LVmN0mr8kmjBTuiTBLNZqbAUyPQ95X7o7z2wBvL
viQVfAQPoZ41ozZ3pC6vXCr3FsIFy1ROWD/95sAdyqlNVoh6VjyfPhRK1tgK7RnPwfDEW9CDiVOd
0t/3CfW83aFyTM9rtC+7e16qfDTcSCaxXzhw+jVdvwYcKrMqi/HYQcP5vrE9BS130AEQ/378CP9y
NiWS1O7F1kXjqsFedUT9AKi7FsZdInY3AUJzZYNlGaLx0/TqlLaD0/yrlABRNHL82AVyCtjn0o/j
r0LR3wiP06BPX0NMlrbofWVDFYshSVr5C0y8z1iLtsAfr0JGy0dJ+KkyS7OQIGhwaBW4lfGF5HLN
qFW7BdNedaMPs6jC0niz37unbCTsyqoGhrZMzcP/YcLIC7RURGvw0iHBRE8i2lqY/DWwCr3tDDIW
Ya+yWDx7Ui0p2tfLlDGDQhCJnqS5kJfMN12NyWfMtfcjKHLPWmI3sFxe5Gint2eFUaUhZGLWmes7
ssNnF0VkAJQRVBy3GqxQR1iTBSe9o0gTo9bSCcLQ0KSuwxW885gxP0P18/LGfn4NTj1h7zVAJ8d0
wClt7QuEjFmJrEBs77PJDL8tQf1uiA1eQDsBJ3j1Q4afQ2rDxKjiCBCflsc9TvjVb5dZlZSnikmK
qRtOIQgHff75P7UE8XkY3UFHrTzseEwdbKlWWhFsiOTH41MTOPHWVPXjSQYgXqUmZ64likqcTbyG
7aSzhxf3bc/C0Vdux6r+Cvq990SU6UqKNGKPfWvLZsyg909j2LDevbfrpnf5f1ZeJ74uW6UuWVwE
u+iYssK0//HXttryND9hm/WkzvkHVJoRvdRuT7u0kwAYtDY/eRKJ+f1+iStGDiUOnPds/KQIMYx8
x9tLBEUD6N1z4PXSnvhuouj/jyIQUtVokk7r59WRgicndlQTC4Mc2oQZCHi0SHIcpsNkkJ/VswPw
FMuuKLIiyyFS+SlTdWsBXgeYEhsAxaFSf3xyAaH2yjjK76i4FJxqUfbV1EOe4u5FbVYx3Mx0DEBx
AxkOEQdrtBcpDcGnYm1jvHtTNjRoOvFo7i05ToOH/hnw+2V3indW0iq38dDIgpOcze+3tZmGxiig
YKjjptzYOm+9xPnsfgzbMRtGKdxWMN8wN3Jgd70sAl1oPrWxZHaXWn4r/W8/bE3vJO6pon9lRkSu
7ogIHx1X/EnGoCFfTsYUzAESuHguO7g2p+yWkzblZ7dKEDAiWxgyJ1Rufg1MJeo4zNmJFM2qdIFP
+h7nmrII4Z+zxf4CTCx9Rp7Txw83rzkt7Mpt5F8m7i06FvFTXEXv/96Aunn/pxk3bd8qYtj16dO4
DpixfS8by730I1vHc4i5J36SKkDWb0SKjlNCFpvgJX9yJGw+5eg7Oey2fQXmwTokrObIneLtmwYh
TDXHBdK5GuvofJsIqH2z7eRhRv+uhCZagsOoTL32btGBRpTA5oQ9GRX4X7zM65Pd3C3r7Ml2Genz
3gwghQpu0iyfWIFPb1k7Nwgl+DG64GCDBrKbgi8/opwJphvtpcWhgXM0+13MTS+vJJ6jy4mMhppl
GeKr4owOQQuLm4ZJGrUd9e+sXJgZx6R1cLKQ7u4SCXQRNUOwkmZ66M8qYP30bIfYg8VO9Uy0VslD
FVlEubTyBhlQVGEet+ebHDzePX6UZQw8xQsw09XaDZMovHBVdUccSUH7cR9TCIAbC7HeZWO9xASh
4IVOPOj2Xh1LC0TN1IgWbq/zBfenLuhiEJh+5TYmyNeSD60TG8VrTDPG9dw+mLvXMkcczXAzUcf7
eqMJ/7jYt4oqU1VJF3liIKTCXKLDekn1E/aE+Ma/cynoubrpj8bu9QBtALuffvSAspYpE+Kow4Jj
sf90eyy/U7IzLonCmXZJ3MMdl29oPHCXzx6UseFtmYP6rZg9mJRjJOytpmZ/a7wqpDf0EaP/Lc+s
aA2YCOjGL9+vEt0S67hQ9Jmvxgi4RLyfp+h282Jy981g8wvPybB2xwwZSwOI4EhGsNXQxw2Q7x9g
N8bikCYw8Jmpw4NgJv/eu9JsCTecS0Suzzq9b3G0UrTDmGOj1QU91lV4KAECjolIjO8HrMwQGnkk
YpPmzwwu3IWRD/WyEexS59mcsSIdfh5BavB/DbZK2I+iZ+sYDFInO0qVqFx4oAAnPbUkPc3uUOLm
J8b/lq5a7ooQlRMt40kzubGnNB++OfRDhoQADWm4Bt2vo2ol5TmX/zOdVYpNUe/CahAWxO/et4OF
h3q656w9ZIFBU6C5LfrmCr9KgVnh702UazEV+JV9D4Ldz5eTyPNnlp3MQpHNuCbzfz7HdvrIpfuU
7FdNIkMK5G3Gpuo1gVFAgwioDmj54m2vrxu8OxJoinUAgX7FNIxegNfD5s7V+JAsEwgh0/YqNT8a
h9zy8gW0+TO+u+4gZN9Bscj0iSe5+WerF2VfK/xryRnwVDt9XSsC1UM3FWHVStAcGnAfcXGLJHul
s1LW9u4fayfCLvkKiVNPJKAxlwDEL8pflftXrQDLFdADnU2pDlzf074Fixpq1an+BQTN//c1WzzH
KK63rbYRrZJoWdu1KsVhmWjulHDOqImdTLBt6gRs+n2dLQQD2ZtHLlMsOjRh/VSXKrYKH9f1l7Yk
P0+0qxwMXzoOCzqtq7Y5Mz+Xv7lZc4G2POLEE8zPzdnEI6T3FitYd+YbrD3Bhk5BM/ANwdikeXdF
vXB+pUj3k1ve8pPW9S4L0rM45scbwQ4B4dhUew4MQmtO+07pkvlt1YVIvQ70h3QLml549ad78a2R
oOb72YkgAfmD1fUO058En8+d/1M8a1hYuPnMzgTvdWW0XQc57AfnEsejPcoGUCJYtWm3nPeJaEYN
XifbwzTf4NIWRg7KJzkNvX2Wsrvi3XtS0fQraOe8YGisXajwYF5/gxLryuIcp0t2sYb8ruiUAkn7
kJVrMemo2XZSKUIrNQ1DcvSzHuaXeRM9WiLGPaXm4JN7XvTY10CDytljotGZQ76MGN5GQyJsIsUe
THi/Hl2PL5vYhtcK/Ukuo5CVWgKBWMH77Ev/1OQCz+f0eljuSgS4qRi3ctnGwc82mXusqgkaV8+v
TK4e+nbwSaSB29ruPxqJMhsZ68MqaAAtc1N+ekKP2oGu8jmvhakiEZm2JBze0FzKE+eioYl4Tkhd
hj39ZxM3PtBoFhs60nhFsLcrIPJT0MNvjw9FDS+vyL6It9N09kDZ2RFo+cvFTc2/bMujj1pk91hs
zTiokmTYwOsNS42rtx+OPJ4X5K40cMUpK2+9ckDaP+3H8xiLa7iYe9ACpcKcnjXl+uf9Cfy6qYjE
8WvdRUkm8x4Q7caPOsHgdfyZRkyiHFmldA0P7f3OCkTXRU//qzryMqjSQDcSyhBSBiIDrW4zao1F
P3qtiErENiIwN7KD4EKEnpmatXoKvEOLA83ldnWAHBorAOQ1FsQR+x75/SBpvAKhjmt3XL6OjQlG
PR1ohsizD7DHJnJTbcLpKlnq2WmCHv/Kol95DrLdh+wjdN8wqF/848jnnyGO/WLgmd5HnWv+OnSt
NAF3NNazRXhwl54rscJ3+aJ3+BYznKUUDpK9BozeKm5ZI+g8E03bamfSJ90RnB/RlUhQNRl8rsd5
/wOxvtuWWANr5k45Y1q21sPQwkvuF0z6R6w5z47160YcjidbcqNAAh8RHJw01W29t26fsDOjyFcW
5cbJTBD3tXgeq5a8uFq+YNyJ3xpKxBS2W3Qq6xOuQSQvcrt+A0DLIL+BF68oPKME6r0lG5e3SMTQ
ffMdKU+bSZ3bjz073Sr0DdH5Yno4kEkc9Q6Rt5YNxKtAC0dQ6Q70DsmmaKe9xkFli5xsh5tWNZJ8
kopVV5vj6gaCDA5lalcZM4OYyqgYxaq6jYn81ot1jQ/XAJplH1rLs/S1vPPIXuh5rWoBqhp09cjF
Gnr5vLUQgMgxHjDFVcUKWWgeqOl95Mbf0ptQG0639723OFfvHhHs02uFHHO/fVK3bbDpn4s+bHyr
qaYlEmoiIxa57ZizVqc9YqYcsEs+y6laQF3OUpJYWCSuhIfQRsRoANOGDi6x/reSeq/2keK/nYUU
hEk78EFrJIG+GPA96GB6qBNFfFw9XoFRtTQ++eCzHf3XQ9DuKr/DoFEjStMhO5GIVwkTavnMzGEH
vQHxUcjvKNm+UT07xZ5ZlhdLZm6rq6PiaMO0Ct9EbDbejBj7iaeKMd5oZLIRZqjNWLvwMjLRlgbV
Ja2JhepqaNb30FTLxWnQJ+Jjer08oSYRpFnC9HLWdxKXnbkEZe8ZAus6Qrm57iQMo6m1xe2SZNuU
N924aM8mzXvAqMioPzI6e2+O+y6xhgY06EUNF6HMvLELzKVlf/jJdj+HM7vB+a6ldYyijyKG7/G4
G/OfMs+s3H13NZAHbG7IiP40fv+rLLANtETcRxcy7RUff6I/UEIj/ScGfj8HOy7mrotEBVx3blE5
rdg64GFU1UrLYY0JsxIpcu4KpDNKMG3EKgR21X/uamvGdcq5PhayqfNpJWm9GdU/ZXo0RmSVGN5l
3vLQpl2rU47he9/dRiCaJuz8yOK1i+lAWTV6Au9kdiYsrPCsQUl3/FOyaCYcTsjPp49K+zk1m62y
3gKrukjDe1XyDG1U7uv2DF/eMLI3tYq3oKFFg6KxrsnEpE/AbPVNOuOj81QUfooaX1caAPx1W+OA
iKkkxNjAOdKT9JdE9DRthXXPpZloLFo0qh3l5hV2J6tW9XCiWmELvMSEdM70mNePRi7x+069mBSo
auu3XlvC2+EtgOUAuN1TDBEG2XjXbuMdX0DGGDVAV07pyDW5+gP+HBjbIBBp7vX84ZK/C1oqhuMZ
/t94DtVz9o52jIMcZP0ZXFnbthQ0FHkGKyMGj+xXJqSBTsQsKjRIkRC+iME5hAxXytPPAVNomv+Q
APeTWRuJm2OeaiaO6hhJOBZq0DieMjWMXb0yr1kscd1X3YjfEc8xTMj1dda9WByHgcFhbx2DdPDF
8vtAjjp5AE9xgRiMYd8+08dopnEDb9ylCw/0JyGTeSvRThOEHZnvrryUrE6NTKoaQxozZVCXokSn
wsHKTuAxaDRhjvXu1JSqtUB0wWtuAuREKJIoqoFvV+3AOjFlx1/J2T87QYIvBAOEylA94z/S+Joi
xBUnX+R58GOVZFMXHojwFcC0oU9643Ih+dXmusnE3vDBM5pOjco4iHt8eCpfc5akl1z9G6YwWAXP
EcNnO2gBeC60pYbRA7b+1IUiQwKKmFbC6OFBYugBALP3sWSptsviqFeR0HgcEuMDJXfVcpTIejiZ
Jq3vFsUXZVye+Ptpx9bOT+wuthmYkXB1OLJ1Bu56wLzU+5OIwejP1Plp+olZZ9xZj7qIKk37b7qS
ghsl076oSqXYehn+EPuuUtJVNs8BZct/k+/FtCTopJ0FMWV8qNFEY40scnoQKxVyDDp/CNuM1Jd5
hsg9/HibvnsL97tN9mtm8QOJFr6G8l8+1z16THYpI1/VjMnQl76e30zBCizru0F0C2+XeTLv29YJ
r1fOagVnhouRx8weWWHIpM8xvQc5NV9oK/IF9HOQ7/5BG6RRyrRGfntym+xa//ZF+7616hyAPhxH
pqO0oN2xaRQz1BHKDx5gRNjD86XaSPryQF17GnlwSJgel11S8AI/Ob1A3/UW7hcf5iAsS0tTrl76
ZDTOMSvCRORZrdAhAVNv76NdiznBkPDvgJOyU14SUZd0mGasktT35gFZCGsK+wTQuyJ5Y2YMtSKl
vGmkYHIy21STldhgJ5ZBHcrRn8mk/M26AXLoOXl5napDBuPE01/e8qb0fjs54JfmXraucfjrO0V9
cJriUm9eyJQ4W3paHs0Ky/KcONfFfFHPIDWAYppdFbzjHqRDh49YE1KaYq/yrKf37t/4tbJ6eyJt
A0hNUkc1uWmwHBtDBpz4yWYpHtV4vKvSYQsqmFoSwPpR18LrD9Nt9mLb1JIRF4cLyHcRcaEpn4xw
fwZkT0rDlpUfTpQBo7+YrciVnehxQum9AX6wXNGiR0xJ2UK1Npl4ak443FK+jnBH2CAu0Dd87NnO
9IzE6QyQ8Mc89rb5X2rRN0okafXQNzL6ziBhIWELyqOQl/oVaChpa8Ssmy+lXsiVZqENSEujHDLV
Ru0sAYlkKdJGPfmKnbjE7dc016oWMXP93s8rZy7cITKnrsyEESavDp51Gk+aVOdwah2JMXn6br0K
HHbQfzJyK6Mqyr+SSW45mMyJ/K5xcAiYJN3Z3OzQ2LO+rlnWHvgMLFVNe/5zC5ruTaGDfHclhP7/
lHtvXSw3lmEhy7cwbW3QQzfIo1bt5s1OI/rBS3xh61sMYdbM0Lg5QML21heKedWlDnQSPR+oQQfN
wHW/OWu8MOCa2C2qHffqV+Y0dJtJewvHYyhqkJtqOql4mOGQj3Yb9D4v3Tj4mtA5syF2QYA/3TbG
/3b29KpWUqx8ISdRtIP670P5M3hOZt6Jc5J9K/2YIbDihwtyAS2x/0e70uuGYGOk9Pp43W9NHJo9
lHtRkyVvEIfqVWq9eYYSQww77G/xSE0NGu/Whms8eL14dXLDZMaHhFd+NSFOROFEvqbBLgSi4YM3
+auQcIAkZHS7k1+qBp8Fpt/hzUWai7tIVcJzs/D+mqUo9EnOXZTS8Mzedqkvv+Aya6aRQy5SZ8Qe
nRu76iTT2hRVjzgrdOcAEXKmFfloaNcGh1ZKolIzuE6BqqYcxJcvScXDyM9eLNCXm5ayUN0+Hmq+
tAuwOc/oRguVPANoxdnGAHB5IA3+duceDr7m7xyXnw6I3DN1jvLVQOqmhmtTFiFJtz923UEuPusa
3gWEUCcZhZupdXbL4tu8lYrJG3mkx/yS7xiGq0zqWsZcO7LKU+yDuDyncP9UalCCg9XAoAWqMEg/
S+V7JFNYN07Sc28oVFQx+V6h2YyLY2vLQ49xwMOWoQ5sHy4WDCmMMXOkS6j7yQn4nLftED/JFn6O
V1SQzA6E1AjZ9Gd7DCY3lnpene4T5W12f2SQ8uTU35HuKJxvImtoHfNiiy4RmfA0Gub06b4TCev8
8AM4YFd7iJKBahQl+cHqIbJRyEX//IAwa3Jx9qxHojSVNs6PMz7ZXuIxgaAuL6TCckx1pUBMcE/g
N93RyaHRpoccRrnXGbJ9V1DLxxQZiMsitT/6pzGcHNO644Byyj/xm/78QCJ5Va5DuKht2J38yYTr
Ql454i687/emQHiQN213O6+B7h0TVH/VDmE/Y0sbjzobAHgLFKhpJbJ7nm9ih4DrB80wNi0Hv1OZ
/HvmuAFvqGP0M+f5pHkj041PiXR6LG/52l2Pn0qEVIV++RBHpG5dD904oJngPLAR2I+mWH0NPXqv
/t+sFo7AM3jAI+U9gkFVBnd/ng3N9i+cZaVZ6UFIRlgV0zSEymGwX85Nm7/1Br893IMwEKpDedc1
69vPgpL4gNU2OIKizYNygwMb+OU9u5Xes3sCTvHFGAeR6DxajgdLG002Fl0t5C8LHd/4I30+uleK
NJSWIhrZGf7RqrwK6Fu5vKgDSM3XBISZbU/j4EfyrVd3z01aCaMPKVQIOULLwd1scHLQxfSvIOiS
8v0CnFgqxG+eTrdZE0nguIwZt+mN5HZoKxp+eEAan7XRU++EkvYWObwL64NAgUk8h46zF9MFKTUj
TcjRnof65gVp+Wi8WxIxJ4mhodafwlC2VCv6xoPrn4cpPdf/QAhL8x3NoebP+rHoYXPwPDiWvujC
kLGUmEnJocY1DWO9xzHSVf8xiyjKLhGjFjZXIkyFlOyLCIKc1JtycICiflBwHFrqfNhugpjPuk7O
nv3OJNKAik6rgzbKjkEbGOwqIyIuuh80G775PH3Bp6HbLGhZ3T06MV/wP+6gUAMO8oWwrliAf97s
r8cGOmgem2FxidTZwwBiH7xZVcvLL/aAeHOHtUopD7X8dK4G1oJtW/BhsoSSOY+6Qmnu3hUqt7LC
eM1Wo7kU81zzJfMp60YQh7+BF3oZmS7AZP8N5APOPDhgAeZghbL7A7r6FJMmhNUOEQ27/Ge99dtj
Bg4Ty3lqIBAvwCvqu+InqxaQR85jtL6JvXBrRyp1NR9Z99d6Xa13RKCBgwLU/UfJ1wkAnxeMHJju
K9M/dE573kjYJ9U8nK8YqP6HNNJA3Hpou+OcYuQXvQZI3YHb5N/YtpKgYY1x0cE0kcjbu//s3Ww5
auRdZ7iA0NIU/AjGwSQ8jdNAnsnG7ik3CAwYdw3L9pHb8ALeutRBSPUoCXs/yy2MRY8RV2CiX3d6
HjFlq+UowgZ7cf23tbBdaoH7uDYYQgSFAvjQQq7j+VQwyTwWR8Gxzw2QTPqfBWc02JarkjP+t1U2
+zYeGqebSBLpswm26MTg+FwQ1aPsI6IaGZP3GNsm47jKBN9Wr0rCQLlMf+XKd3KqYp6C7O+g/r5x
vbO9jaH751NgSMvsube84WgNna9oWQoYK3zJ6lf+RBX9S6R4zRwrJuvGYUa9MMNBnXZktmqSI1El
A0qQ+4uWtnTeJDRXyO5M05Gu3ebjiQPSj0r1LKxWKfkTIJs1TwP92CWlXaFSnWm/X1nf4zU96J5w
I1WYnQva9U7zGhqlXYsMHTtDn4OgIt09xJvrPVq5rkZl5Ka0RR4P+C3pS7FRkM7a84r4429sZqn0
1bF6vnTOmmnCDZ7+rdk2HGPn+KJudOLwHiWztZjCvQsuss9DENJQUyUZ3XCUUoTojKzDPIu1cdRl
T6jkCaoOJrBadc0IOBhSb77aEFckFo/Rj78xGGuS8de0opqgN7lvJUEbdYrGMFA2NcPlsFm2vq+3
ljHFQ3CX+AWQjtZJmqIc9g46iLxhlM9aZBOd6V9d19c8lqF1ag/2yLEP4HPvz0JrcCyNrgxCL3qR
l1lCR9gLhHW8EgrIQ2qGP4K2WQUbx2+6oarcwCqjJMkoP+TK7pr1Kc6U5cPB5uzOUBSn5f1cOYj8
k7QIxk8YYO+15GREfYvgeVR2Sh5Kev1e0BqU5J1UYFZNUjIazwCh6xNx+ulSA5SEqX/+cvvI2/xx
s+iBLfw72I2wa8ni0GucIiXioee4NDlGpFVncEbNdtlNA/7GgbSwlNfhBn1RCWAl0PHPHKar8WRp
U0AOS5kPgPZgaMc6I2sTmyItWO9TNRUgmtswr1VA8FUE2xsAzSqSiBnkkiCjpco6M9SaF18xlW3y
RgLQ3m7FVwVTCe2L2cuY1trC1sL5q9oIR26m7XKrmZU4EyeqF9cD/E76sU9JnNrFocMSvfHUXM2u
uxY3FjeuNV1jqsrk+EHlySoxb5ZnnEOHeGGbNUCwHBwIsAXyTUuzLQHYYMR/YzZwPWeespMc8gUy
PvY7v3W5bvx22x/xIBo6iac7S0wYX5MhIkm4pKanP6pFysvPBUOsOjOIEsmz2NZn3ENQzw0wHv4g
BQmz/PtwBZNRANk6+apM+z+s8fIGCh6aqXspxi+1Yvbi2aYl+W50tAZvJC8gwedDmkLg3iMnRTRU
AWi/buhLajU7Hx1cA56LKM2ToxXochWzMX6y5g+8a0SRy+5bzpU7dUMLaGIEVWT9brMftcpfwYJY
aLnAZ6qzu28CkV1axL46q68JARkl3WgUywezNa41PEtzu6y2eVdIr+YVT8/n1Wfq+PaKrx/7UGuQ
Apirt3+2gFoVmhBMsqO6it1xhM/H94hLV1D4ebiSGa85fViQssHrb3nxsTzugXJCTlyw62Uh3zhg
Sh2MxusTuJOR9ErKgQBi91iSV89pw7LPCfTG2iRVT3Ld7a46R4S3lQAqk27qEkh/eGePHIM7e3vo
ZJ9Uf6PdcGf6uitNuUmKS1FwDoylaSU24ajZTv3RXBpIcvENSjNz/4jX5l4rZgZNTuGokttCbpZk
2eSYpafCz9pUJ5iDbguS1U43llStZ0G2ue5JZBhP/CwtQlAjqWZ4URX4Oeeb4zkfKx7U5D/emF0A
2U0uxkyUk4uWhZ7W8J1dsM9JZyW/ZvclHyOb5MfLXb5MShTpCe70Wf+AFMZKI11IeVEQ9EC9a33C
lnZIHj1CDPNm1TSfYe6VxpFffwG2vFtrofBzD/if3gaxjPyPknpjObS0py0c6qiot+8AgmYATsN2
FLe0PkpAyyiew0wJK7C1Ci1ST5epqai8J3JmXUQ9ppfUFqNbdDPg5LuQqAPDn/pcjHrsoQos/cda
rL/8hhDyC29qOTTgnuhxN8glrPSyMKkH2jlVb9FhFyqAuRvlL6aOeHeEDSiFf5LS2kJBl2cPLhkz
IxGL2eTWzC9J6LbHMYVjqxzZETL5gYGPlJMWq5ZxsTEDxeyAg3TcjJZBmE8qQ6MEVk8xMCN5it1x
u/D04kzwKNYztrIRAZYGBkCd6ezig5z6HAQSFidxK8sNEO7mb1Teiq0tz3OWtva4bPPmUo6pwG5K
jyL1ThjafcvRNWaucI+fic1rE8JGve+Jm2Q9abL9VJ9ZXKNkCS9ZCmmIACnQNF7xgv3Ik+hamNu7
gqGGALxtH+6LlaqVlme6EhK1GePC5623W8rmI5SKxRIuVZuS4W6z9p3rUP+TajEkELLzJKtDOoWQ
BM0lA+n4NH2VGnBhU+ooh7TBAMVgeNsiIgNg4N8NIHVM0PK2ccRyaqQmMGZGKq8yWVp6obeassH+
VaG4GQ8JGEoZAXrfeZxsz7Ofzi4jCYQqx6IPRp9HiWcXIEcHBFEL6oY0XkwE6pd/mCt4wcBLBg5J
u+6F51/DsFYdbJBCg4Oilku4zUUBj8R4zn/2Bx6laq3y5JrxfcqUq6pIcQae4t2uwbHSIGjTjrH3
jd1NNeA3Jm68GfI1kO9QLHVdisY4sq+8yOkyOJBDzPT7B7MRxWIgIQ+MiaNb07bhrZXzAyYxLj+n
F6cJrwESbeGYXraiSX3Q4RIGxNmTgNvVo1P5Xgz3goA9Fy5b+SdZKQz6dXciAMrLct64iYTthFmk
L1MYzOKHRpYtTcuEyEXsQcfmQTwSP9//BNvt0TM9QGBAbFm6XXswaxjxxxG0rLoZWT8M167mzi5w
VRoM1AKuNDMQGVf4l0vegZVw4e3rfVJsTcthXKvBDfDKBLf6yX8cAZlZUo9C5O5AU0w9H/xfX3aU
Wz0UTD7bwmh/NUIu5i2DzkYOmCcgVJMtnrIWdi2MG8EW5T3PkXSdJq/D91yeQK+gDQaRDRLFUqnw
G0Nk9YPc9EIrS/gkqZv83AaN7g1fQSZqzXReSsSKxvey3WWeqaOIVEgciN2EB+k5L0lBlf11n1vo
5yCMpJqiwqm8ZgoytWG9zpZ1Z/hlkwvdGgF0VRdoOYnldbKW/vMdd4ZUSUuJff4jUZL/feYuaBMR
FP6hwbySwclA/gI7IN0xtQ07ecgObG9ciRfq9kIlUx4yyjRQVt4vnp6XKokx0Eo1+OS/kwmWUKt0
bsfLKgKq97+7fBct8Ic5YKP+bYBBj6Zy5zHlzFnlznv0P+wfFlya+xYrx8huuKvXoLd7I9bAsOvn
tU0L4vZQBNAXSYsS352qfqZHOYEFcZY+9+HNuYIqUbp+EXjJHZTbWJ920rvd+tOPOdsQYFftXsr6
ebgdiPI2RucWNBCM255kt/aB4xchia6U/VZ+VdPWkZOzxCo0l2+kCVQzGF00eQkOUPmGAqlC9oAO
VaRZJZOKj2IZ4c3Y9JZfCr6aiusMzdacXaUjMRepCvEnfhWN95QNuZKc5YpVGaPqKXFGwzeZNhRH
iGOvJF2/7fkYiAV8B89jTp/UoP4FTpBCnl4cgCRanb+bxE5/o/pUXxOcsHh/8rFuIrgZsmcJP7Br
6CtfYDu84rByqx229ung6LNjPbzJSf85F1xX6gCpDUoYy35dORr4/sWy1LVynq8SyNdccSHiNAK0
YUu54dY0mfnDezax+xLG8TkDL50umGa6DcwtYKqiVs+BXRcTa82KiwrOvCRpzx7LZowCVkpZoHdX
7eSEojf+sns04Vb2GZdGD6hJMUFHBxVGqaMTIGv83frR33ENpA5rhFF2LGDtH/kb1p4c7ZVPM4hH
5MWn+y7jqDLyDaAo3DpfRgwR5R7OY6GIKC+tP3W0SafZuWcAxXEV/Yez7UYZozedgbtcKlBuy4Qw
TVpdpTikNB9Z0+CH6CGOWeP7LEduViMdhlNK4Y1ISklVZacjaW7VFk4avS40CLnBIZAt21SikZaS
ED8Dsf3kSBVDlyYmTLwx6ujjbrtkdWSzeAI+n2E3xpLJHewEdD2j8blobjPEifPm8Z5JvLkfex+9
SVopTg+iCWFQmgepixYIZ+LwEAHMWfDrhe3JTndUyiAsVr9hnQGvDMqNGR6MGxk4J1UdqcGY4MQg
WFaQ/NoHY5xsUSbnFn9o7EBHE+vupnbxuSCPGHiHCY4jdrhqUdyD/kdfrvDrUz88UdWKBS4lG/VL
UjBqQPGS8Idnosr4BMqW3AW2drCY3jAJxPk1XW1JuZ4BMx/H115Qo0hlBR+5mtBAll7XIJ2XvYOG
u70CzHeDQXwmiJCaSJCUIEWHudO3JMhJGPjD6WJBVNN/3MJiNzmYQGYvrZIDszoYbERJik1REHnY
yJbzD675PfsdWj5JXjs+1kTagbDDDt5LAWCyIJBtTJ2XwGI7QTgK/2yKKbSg/CJOwwZuR92gjxkY
kLePqYwlL5cEAoRBYuX+aZW/f6ehTlnI3Y0anEEHij4d6FbvQXEEl86zq0+sXzFSxRC6P0a2nYdC
tRrpfjMMbZj1aiNk2vB3oda7La/Ytk9eEbjmCxvikHSRYUwrKrBheC1gRKKBHdwR31TsULHqFVKi
3tKKPaMi1LNom59HGnPHrOUchk83JKxpkhZbbOhpGCTKXETL/3XPU2smaDE3m/065OAxlIS3ojpS
30Alw5ys0ZhKyKSHFmNXPKK1GPIScvhHi1FlQE5i6NUFHltOm8wfhzn/HqgsbbCKVCeyrXD9wgFc
+yKZOQRpjKMWe4D8TkfbSCEt/9l/n3nJUoucDDg+mSRIYuGmeaMpV4mnrPEvRLG2un2ZyYykFPkR
eRon9e41D0GOHbWhRWtGKGfUpCUrlIvCUY7D1JOBP65/cEJtcQzwbHN0ofY5yK4RH8cXDUhDnxxW
MpnzyUPDM/nyaLftoSDefXpQ3/Flk5Yi0yrUyiSs1wgqEh6gnefmSBJGM93HYSSmh77sLtP6FTBA
zJaFtCZX4PsN4vm7PNbgXq8VYe5y0kiQcBbgZWXvxYqOerMN1p26m4E3uv56VhNkmoq82TeUt2Lt
evrn4yoqUaq6ntDlBxwuM/fbAIW/HnLDzsbkGLYHQOLdxh7C6581VRsuh/4c5vEfaiEGbZTRuQVI
JwbBabrNhr2V/D5T98P6F05aV/PtazwNnu125zxyXitQ75cmw4bBDlrkAwD05Cm+YFbLbrh7mnZH
3+O5pYzRAKDaBzUFAm7+Ny/+N9Koado3XVR8bmXfhWwtmOG8eJUFDpHThh5Nn3D3MBDyKysN7L33
NXy4DlfpkrTFP3PvQ6MkmaYlpvkDy/HXXBZiNx9YJGgQC5vbBPICHCEDSCaO+tAawpousPXFzrmE
f8i9K+ursZfbACRfh9q6/Z5ons9gbQI5JPVY9bawZgcjJQn8Culfm2z58QDuLins1lk/x6RVnj1o
vJ3vkJuWiK8s8rXG/Y8DVFR3n6kRIuJ7cqHQQVSRegAnK10BzV6uK00m1JQelL90NdirTriMqETC
QnqM2RTEngHcPosZaC3ROB23RHN3spTgThYuTo0RltumHg3qEHLzTeH6UKaCUm13cVVZCmFcX4gx
DbJ4mhtLmWubR+Oaed5/mojMt9vVFpOgTk0KM70jd330mbfASt+xr+y56bm5IEBZLVvuju3F6kY5
N+ggDqYd5c1Ix8XTpmpQAUifrD9SWmWVmqfDyhmtSRTR98nrheXmnJbCxzUSQhGG3vwoVG6gSBDx
GsJWWFjSr7wJbK9feyKcyPZrYyxtYA7onXMqO7m5UUKc2GhjjtvJ6IUcz6XMyHWBeUGyV5do8d6R
/pK3umTIDsj+Nct9Hy0RQHe9tsmhw6PAF+IuOJ3V0Bn/l1M6WmTn86tlzMefCRDPI9qPjQ6/rc3l
ReZ7plrZ+C4bcpb18NOeL0trsR71VZ6aQ9e99zoXRfPiqSMIoFxKhCTJ/ziaCkNcdsvLfQpZx9hW
mk64qO6AKe09Uypg2y6TegQctzpHGdQip+CBAd5mwKmoCAPLwW30l0gmaEXelz0ZN9STyV54p1tP
YRYC78B0+dTwPOePZUqd7+bJsBMv5aDZlE9vY35x/NVUGzp8jDypxaImcLZRa8jIToP3eHdaMymp
qPmxZxBkImHjh5GA3QkD++rwEDpCmrGx9pGJKr5VjzMZAnSZ2OBVs1fCRSdn3ViW+hT0aT2Rw3jB
bnjzZCgbGxwax8JDeaqBIDFK9oKVrAX97dItUlBYrHSiH7IlN7pEqVZPNhW6rPxfn9scvOhpUajy
u8xf4qpNfT+OCBbOscxodNaCiDwVH2H4I7+Zv9VgER6PsZk1WLUSV3lGjWn4YiVDLOWv++qbFq7l
TKnskh1fyd5F3fWMSrCGbDgrLlovH7OnwE5xqrc4+RiRmSDt49BxSA9FZ0MegTpYZ3z0xWa0UTBp
DasxTBAXYiJBL1CHHa2WLGuDHUbWmy+67E+JWGasMTW0aSuhly0izQ/0hs+JVpnz+gqbusL1WigA
7i+0sxiC9klIr+WzkWpYbPgTfjn/DDIMjoGg7cC+95QKY+YSK2MWCnM85MnKcmPntt8ED4xxrU6K
Kbe/EuVAVE09rrE3ZwnsTmeu3IxrQuDCJy4zpcix6wSma6YYqsUaCoeZzghFn0/DHv5NyMenKRHs
kG8018L7rg8E2Jrg6ZynM1ZP/zP6qqtjIrQgJnIJwOVrIMjn6tT6XEA38XER2vp9q/8UUEb6YXAF
RZpcq+zuJXoasWhA6NoEZYKW1IHc5ILp6xg0lt/Lf9CzOJnxIUWnq1PHE2gBQUkvxDtqELN0QLyC
tmwbD0I3/0FukIQno9lGkTpefqIGAX+vF0yo7RGCGoWHP3JyWbr4nTyF3quq7I8FhhaTq5INixZh
CFDw3u+turWpqyhtvlU8ua3VgvUunJa05pIT8YkH4mOaRsxDgfugR7tcw37paHbp75ejsGKlL732
JtoKb8MNwBXIeCMSB2ETCo+pTNAnHKbC9NxagqEogsIL9XGQ6gEUqwGAvQzXRWEFl4YD8xupI7GP
41ul+Lbk0mpRtpheQyk5fBsBB1Eqgv8ah0qyZkZyiLqbMvxHlxbK/G7OA5O0XuMVybJyyVY/nEIP
gwFHM80/M7Wz4QlfIxRTnKq8Y9iKordO7Pcf/T7nYvepwttCB8AKBIW73oT0mcpOSErhAiyNSt1i
xhBTWm8580waiHLyc/3RsvH2r2l41IoG/YEQItCGq3MOCOjh4X26GHzLsUfQ0mic8Wr8dvapaNq3
gKhAO8/Py3Vc4J/nYqqsaWq4hRcrMLwY0SRGotIK8tcy2z0Qe5EKt0cJ3a4GstdBLQc7QpzjESDp
rjS3fomMC8xpQxiwDJkg9BxkVsH9tdqCxBT1feiSCTZv9cl6ZY5oKsgDowerj30aUxhUUwqV1CiF
oVSLSvyRIRB7rbZNX6OTyXloLx4ZfIlDUh5SVSyZlU5Pux5NvqmfCtt/dhrPwNxPmrcGHspLdMYA
AnYFObocya+3mSi03hznynlzXYnPCVO1TrrlMG5veeALLu01XXrL7bWf8iq2b/0VOH+CXAsJkLHB
1gG13XjKEUNaP1KSGV7yCrfa7T/EnZkgtyWGDm7G9sV+tHRL5zJtBABvarmvxnfxoPDnn9L1zdoB
ZLtEz+7TK/kQ9LejBZoWNwdvOlUJFaS+/imyCV07+vFp1FooSUQHA7ChUI09GMZSqZzYXzn/XkCR
pA1Ni8HIzFgrDxxY9rb2E/Evyz/9JjANn455FAYsRqpdnxTkntG3z4DrQC+GQlNubz3KjvezNCXJ
4nr/6iYoaT7gdcESZF+jrZgcuICk/NKy4o4aZQLSfkunLkEqJzuQ2t5hltBLMWP8qP8zHu839QKn
aKWo0tQwAEDlf9p66Q2Ab7uiW2qnR88WbJep6boI+cv1XQ/dM7IEfT4SM++nPkXk9Kb3IwbEn77C
dG2nl3MM6nsCxEQexLcRJAl/ja+NWpMNk/rkD+W6xSc/ukwyGrd7lYu/lhRXd2ZWBn+KUBooU3OU
pc+Uof18yXI6GsFT3a+vOa9rE+CuCkgKgRp4LOR7yExIOMZKsWRFqEOBoogw4/Q0+ullxN+zACBr
id/1Jyur/I/9umQwcUgjISr+TTBZNR8rj6J5I0ZV9dRA0LglVWAdN9gRuB2S7hkBMgG+6oKbwWB0
QkPABtVKKbp0ZQO5bPciSrTMBalfIIn+Jk6C7vS0GhPktmZFKFlZaX5WNbqxZ/rT2v5FCr/M3PVo
g+aZYxMh+ZwvNA7Hgu8vfsO9McRrQRmyRXRmPQCFI65hDG3krF5oIEHK26qvS1B16vIXlJnLtK31
ji5x0UZNVVU5QZGlwm2Q3e9FyjE5R8Fdfyt3Zeo2KvZ8f70YM/ilp9ZvwPS93UaXqR6bh/dumHKL
fIspme3CdFi2N1KL+//4X+gnpIVOw/4A3wsdYVyjbENqzkIBkd6lb7Acq78DXNqpu9tm+fBntxyy
/iXgmItOcc8yb28HGaOaihCcuh/Sm7ce8bsXrCLvHs7bsDICsy90gKPZH61O0MYcWz6QmbLblGjR
/wmPJIVj4SL9tRXIUF0bSvLlYlI6iOTmdZwrxTZTJjsYRCjH4nkvZjLZSwzPO6NzJE2UiV04+CKy
rqNzKA0aYy8LoxPz0RszmebYoe8OSqAD/mhg5nYYF517juQnK/jvQQQJrdv6W3rmzPI+aeod4+jn
fm2VxqDvtWYzV8WYTsb1cB2gg4S1HRjhtyfGQAypWG6BPCfaugXJBA0oy0uHpSkltnxGzBCPJdUE
qVRmFQbTzODiU7hnf7rCOAvPPp9lqCn0BAjafQnAWstgqD7PLT0l1Q7/C8oCCCzWAUtaDOTRBOBY
+DO9aImU9O12Ia8FpYtloJfBNGxTASQqdRuBn1T+7gjtiEn14FpOTnA5+OmTn9bCGgxlgN8i/eJk
jXi+
`pragma protect end_protected

1295
gowin/seq_light_test/impl/gwsynthesis/seq_light_test_syn.rpt.html Normal file
View File

File diff suppressed because it is too large Load Diff

46
gowin/seq_light_test/impl/gwsynthesis/seq_light_test_syn_resource.html Normal file
View File

@ -0,0 +1,46 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Hierarchy Module Resource</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
div#main_wrapper{ width: 100%; }
h1 {text-align: center; }
h1 {margin-top: 36px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { align = "center"; padding: 5px 2px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="content">
<h1>Hierarchy Module Resource</h1>
<table>
<tr>
<th class="label">MODULE NAME</th>
<th class="label">REG NUMBER</th>
<th class="label">ALU NUMBER</th>
<th class="label">LUT NUMBER</th>
<th class="label">DSP NUMBER</th>
<th class="label">BSRAM NUMBER</th>
<th class="label">SSRAM NUMBER</th>
<th class="label">ROM16 NUMBER</th>
</tr>
<tr>
<td class="label">seqBlink (//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/src/seqBlink.v)</td>
<td align = "center">40</td>
<td align = "center">31</td>
<td align = "center">23</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

2
gowin/seq_light_test/impl/gwsynthesis/seq_light_test_syn_rsc.xml Normal file
View File

@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<Module name="seqBlink" Register="40" Alu="31" Lut="23" T_Register="40(40)" T_Alu="31(31)" T_Lut="23(23)"/>

13
gowin/seq_light_test/impl/pnr/cmd.do Normal file
View File

@ -0,0 +1,13 @@
-d \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg
-p GW2A-18C-PBGA256-8
-pn GW2A-LV18PG256C8/I7
-cst \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seq_light_test.cst
-cfg \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\device.cfg
-bit
-tr
-ph
-timing
-cst_error
-correct_hold 1
-route_maxfan 23
-global_freq 100.000

21
gowin/seq_light_test/impl/pnr/device.cfg Normal file
View File

@ -0,0 +1,21 @@
set JTAG regular_io = false
set SSPI regular_io = false
set MSPI regular_io = false
set READY regular_io = false
set DONE regular_io = false
set I2C regular_io = false
set RECONFIG_N regular_io = false
set CRC_check = true
set compress = false
set encryption = false
set security_bit_enable = true
set bsram_init_fuse_print = true
set background_programming = off
set secure_mode = false
set program_done_bypass = false
set wake_up = 0
set format = binary
set power_on_reset_monitor = true
set multiboot_spi_flash_address = 0x00000000
set vccx = 3.3
set unused_pin = default

BIN
gowin/seq_light_test/impl/pnr/seq_light_test.bin Normal file
View File

Binary file not shown.

BIN
gowin/seq_light_test/impl/pnr/seq_light_test.binx Normal file
View File

Binary file not shown.

BIN
gowin/seq_light_test/impl/pnr/seq_light_test.db Normal file
View File

Binary file not shown.

1378
gowin/seq_light_test/impl/pnr/seq_light_test.fs Normal file
View File

File diff suppressed because it is too large Load Diff

29
gowin/seq_light_test/impl/pnr/seq_light_test.log Normal file
View File

@ -0,0 +1,29 @@
Reading netlist file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg"
Parsing netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg" completed
Processing netlist completed
Reading constraint file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seq_light_test.cst"
Physical Constraint parsed completed
Running placement......
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
[30%] Placement Phase 2 completed
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.power.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.pin.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.rpt.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.rpt.txt" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\pnr\seq_light_test.tr.html" completed
Sun Jul 7 15:45:27 2024

3537
gowin/seq_light_test/impl/pnr/seq_light_test.pin.html Normal file
View File

File diff suppressed because it is too large Load Diff

276
gowin/seq_light_test/impl/pnr/seq_light_test.power.html Normal file
View File

@ -0,0 +1,276 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//ENhttp://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Power Analysis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper { width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td {white-space:pre; border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.thermal_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.Configure_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table th.label { min-width: 8%; width: 8%; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#Message" style=" font-size: 16px;">Power Messages</a>
<ul>
<li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li>
</ul>
</li>
<li><a href="#Summary" style=" font-size: 16px;">Power Summary</a>
<ul>
<li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li>
<li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li>
<li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li>
</ul>
</li>
<li><a href="#Detail" style=" font-size: 16px;">Power Details</a>
<ul>
<li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li>
<li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li>
<li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="Message">Power Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Power Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seq_light_test.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.9.03 Education (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sun Jul 7 15:45:13 2024
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h2><a name="Configure_Info">Configure Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Grade</td>
<td>Commercial</td>
</tr>
<tr>
<td class="label">Process</td>
<td>Typical</td>
</tr>
<tr>
<td class="label">Ambient Temperature</td>
<td>25.000
</tr>
<tr>
<td class="label">Use Custom Theta JA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Heat Sink</td>
<td>None</td>
</tr>
<tr>
<td class="label">Air Flow</td>
<td>LFM_0</td>
</tr>
<tr>
<td class="label">Use Custom Theta SA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Board Thermal Model</td>
<td>None</td>
</tr>
<tr>
<td class="label">Use Custom Theta JB</td>
<td>false</td>
</tr>
<tr>
<td class="label">Related Vcd File</td>
<td></td>
</tr>
<tr>
<td class="label">Related Saif File</td>
<td></td>
</tr>
<tr>
<td class="label">Filter Glitches</td>
<td>false</td>
</tr>
<tr>
<td class="label">Default IO Toggle Rate</td>
<td>0.125</td>
</tr>
<tr>
<td class="label">Default Remain Toggle Rate</td>
<td>0.125</td>
</tr>
</table>
<h1><a name="Summary">Power Summary</a></h1>
<h2><a name="Power_Info">Power Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Total Power (mW)</td>
<td>124.846</td>
</tr>
<tr>
<td class="label">Quiescent Power (mW)</td>
<td>121.198</td>
</tr>
<tr>
<td class="label">Dynamic Power (mW)</td>
<td>3.647</td>
</tr>
</table>
<h2><a name="Thermal_Info">Thermal Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Junction Temperature</td>
<td>28.998</td>
</tr>
<tr>
<td class="label">Theta JA</td>
<td>32.020</td>
</tr>
<tr>
<td class="label">Max Allowed Ambient Temperature</td>
<td>81.002</td>
</tr>
</table>
<h2><a name="Supply_Summary">Supply Information:</a></h2>
<table class="summary_table">
<tr>
<th class="label">Voltage Source</th>
<th class="label">Voltage</th>
<th class="label">Dynamic Current(mA)</th>
<th class="label">Quiescent Current(mA)</th>
<th class="label">Power(mW)</th>
</tr>
<tr>
<td>VCC</td>
<td>1.000</td>
<td>0.863</td>
<td>69.994</td>
<td>70.857</td>
</tr>
<tr>
<td>VCCX</td>
<td>3.300</td>
<td>0.548</td>
<td>15.000</td>
<td>51.307</td>
</tr>
<tr>
<td>VCCIO18</td>
<td>1.800</td>
<td>0.543</td>
<td>0.947</td>
<td>2.682</td>
</tr>
</table>
<h1><a name="Detail">Power Details</a></h1>
<h2><a name="By_Block_Type">Power By Block Type:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Block Type</th>
<th class="label">Total Power(mW)</th>
<th class="label">Static Power(mW)</th>
<th class="label">Average Toggle Rate(millions of transitions/sec)</th>
</tr>
<tr>
<td>Logic</td>
<td>0.288</td>
<td>NA</td>
<td>13.206</td>
</tr>
<tr>
<td>IO</td>
<td>5.886
<td>2.553
<td>30.000
</tr>
</table>
<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Hierarchy Entity</th>
<th class="label">Total Power(mW)</th>
<th class="label">Block Dynamic Power(mW)</th>
</tr>
<tr>
<td>seqBlink</td>
<td>0.288</td>
<td>0.288(0.000)</td>
</table>
<h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Domain</th>
<th class="label">Clock Frequency(Mhz)</th>
<th class="label">Total Dynamic Power(mW)</th>
</tr>
<tr>
<td>newclk</td>
<td>100.000</td>
<td>0.024</td>
</tr>
<tr>
<td>clock</td>
<td>100.000</td>
<td>0.291</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

3793
gowin/seq_light_test/impl/pnr/seq_light_test.rpt.html Normal file
View File

File diff suppressed because it is too large Load Diff

345
gowin/seq_light_test/impl/pnr/seq_light_test.rpt.txt Normal file
View File

@ -0,0 +1,345 @@
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
1. PnR Messages
<Report Title>: PnR Report
<Design File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg
<Physical Constraints File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seq_light_test.cst
<Timing Constraints File>: ---
<Tool Version>: V1.9.9.03 Education (64-bit)
<Part Number>: GW2A-LV18PG256C8/I7
<Device>: GW2A-18
<Device Version>: C
<Created Time>:Sun Jul 7 15:45:18 2024
2. PnR Details
Running placement:
Placement Phase 0: CPU time = 0h 0m 0.01s, Elapsed time = 0h 0m 0.01s
Placement Phase 1: CPU time = 0h 0m 0.529s, Elapsed time = 0h 0m 0.529s
Placement Phase 2: CPU time = 0h 0m 0.012s, Elapsed time = 0h 0m 0.012s
Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Running routing:
Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Routing Phase 1: CPU time = 0h 0m 0.254s, Elapsed time = 0h 0m 0.254s
Routing Phase 2: CPU time = 0h 0m 0.283s, Elapsed time = 0h 0m 0.283s
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Total Routing: CPU time = 0h 0m 0.537s, Elapsed time = 0h 0m 0.537s
Generate output files:
CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s
Total Time and Memory Usage: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 439MB
3. Resource Usage Summary
----------------------------------------------------------
Resources | Usage
----------------------------------------------------------
Logic | 55/20736 <1%
--LUT,ALU,ROM16 | 55(23 LUT, 32 ALU, 0 ROM16)
--SSRAM(RAM16) | 0
Register | 40/16173 <1%
--Logic Register as Latch | 0/15552 0%
--Logic Register as FF | 36/15552 <1%
--I/O Register as Latch | 0/621 0%
--I/O Register as FF | 4/621 <1%
CLS | 30/10368 <1%
I/O Port | 5
I/O Buf | 5
--Input Buf | 1
--Output Buf | 4
--Inout Buf | 0
IOLOGIC | 0%
BSRAM | 0%
DSP | 0%
PLL | 0/4 0%
DCS | 0/8 0%
DQCE | 0/24 0%
OSC | 0/1 0%
CLKDIV | 0/8 0%
DLLDLY | 0/8 0%
DQS | 0/9 0%
DHCEN | 0/16 0%
==========================================================
4. I/O Bank Usage Summary
-----------------------
I/O Bank | Usage
-----------------------
bank 0 | 1/29(3%)
bank 1 | 4/20(20%)
bank 2 | 0/20(0%)
bank 3 | 0/32(0%)
bank 4 | 0/36(0%)
bank 5 | 0/36(0%)
bank 6 | 0/18(0%)
bank 7 | 0/16(0%)
=======================
5. Global Clock Usage Summary
-------------------------------
Global Clock | Usage
-------------------------------
PRIMARY | 2/8(25%)
LW | 0/8(0%)
GCLK_PIN | 1/8(13%)
PLL | 0/4(0%)
CLKDIV | 0/8(0%)
DLLDLY | 0/8(0%)
===============================
6. Global Clock Signals
-------------------------------------------
Signal | Global Clock | Location
-------------------------------------------
clock_d | PRIMARY | TR TL BL
newclk | PRIMARY | TR BL
===========================================
7. Pinout by Port Name
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | BankVccio
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
clock | | H11/0 | Y | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
led[0] | | N16/1 | Y | out | IOT52[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
led[1] | | N14/1 | Y | out | IOT52[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
led[2] | | L14/1 | Y | out | IOT34[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
led[3] | | L16/1 | Y | out | IOT34[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
==================================================================================================================================================================================================================
8. All Package Pins
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Loc./Bank| Signal | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | Bank Vccio
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
L15/0 | - | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D16/0 | - | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E14/0 | - | in | IOT4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C16/0 | - | in | IOT5[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D15/0 | - | in | IOT5[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E16/0 | - | in | IOT6[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F15/0 | - | in | IOT6[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F13/0 | - | in | IOT8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G12/0 | - | in | IOT8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F14/0 | - | in | IOT9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F16/0 | - | in | IOT9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F12/0 | - | in | IOT12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G13/0 | - | in | IOT12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G15/0 | - | in | IOT13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G14/0 | - | in | IOT13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G11/0 | - | in | IOT14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H12/0 | - | in | IOT14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G16/0 | - | in | IOT16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H15/0 | - | in | IOT16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H13/0 | - | in | IOT18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J12/0 | - | in | IOT18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H14/0 | - | in | IOT20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H16/0 | - | in | IOT20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J16/0 | - | in | IOT22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J14/0 | - | in | IOT22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J15/0 | - | in | IOT24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K16/0 | - | in | IOT24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H11/0 | clock | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J13/0 | - | in | IOT27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K14/1 | - | in | IOT30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K15/1 | - | in | IOT30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J11/1 | - | in | IOT32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L12/1 | - | in | IOT32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L16/1 | led[3] | out | IOT34[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
L14/1 | led[2] | out | IOT34[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
K13/1 | - | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K12/1 | - | in | IOT36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K11/1 | - | in | IOT38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L13/1 | - | in | IOT38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M14/1 | - | in | IOT40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M15/1 | - | in | IOT40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D14/1 | - | in | IOT44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E15/1 | - | in | IOT44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N15/1 | - | in | IOT48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P16/1 | - | in | IOT48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N16/1 | led[0] | out | IOT52[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
N14/1 | led[1] | out | IOT52[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
P15/1 | - | in | IOT54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R16/1 | - | in | IOT54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
A4/5 | - | in | IOB2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C5/5 | - | in | IOB2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D6/5 | - | in | IOB3[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E7/5 | - | in | IOB3[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A3/5 | - | in | IOB4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B4/5 | - | in | IOB4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A5/5 | - | in | IOB7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B6/5 | - | in | IOB7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B1/5 | - | in | IOB8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C2/5 | - | in | IOB8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D3/5 | - | in | IOB9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D1/5 | - | in | IOB9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E2/5 | - | in | IOB12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E3/5 | - | in | IOB12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B3/5 | - | in | IOB13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A2/5 | - | in | IOB13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C1/5 | - | in | IOB14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D2/5 | - | in | IOB14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E1/5 | - | in | IOB16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F2/5 | - | in | IOB16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F4/5 | - | in | IOB18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G6/5 | - | in | IOB18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F3/5 | - | in | IOB19[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F1/5 | - | in | IOB19[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G5/5 | - | in | IOB20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G4/5 | - | in | IOB20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G2/5 | - | in | IOB21[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G3/5 | - | in | IOB21[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F5/5 | - | in | IOB22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H6/5 | - | in | IOB22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G1/5 | - | in | IOB24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H2/5 | - | in | IOB24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H4/5 | - | in | IOB26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J6/5 | - | in | IOB26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J1/5 | - | in | IOB27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J3/5 | - | in | IOB27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L2/4 | - | in | IOB30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M1/4 | - | in | IOB30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H3/4 | - | in | IOB32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H1/4 | - | in | IOB32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J2/4 | - | in | IOB34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K1/4 | - | in | IOB34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H5/4 | - | in | IOB35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J4/4 | - | in | IOB35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K3/4 | - | in | IOB36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K2/4 | - | in | IOB36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J5/4 | - | in | IOB37[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K6/4 | - | in | IOB37[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L1/4 | - | in | IOB38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L3/4 | - | in | IOB38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K4/4 | - | in | IOB39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L5/4 | - | in | IOB39[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K5/4 | - | in | IOB40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L4/4 | - | in | IOB40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N2/4 | - | in | IOB41[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P1/4 | - | in | IOB41[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M3/4 | - | in | IOB42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N1/4 | - | in | IOB42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M2/4 | - | in | IOB43[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N3/4 | - | in | IOB43[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R1/4 | - | in | IOB44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P2/4 | - | in | IOB44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P4/4 | - | in | IOB45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T4/4 | - | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R3/4 | - | in | IOB48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T2/4 | - | in | IOB48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P5/4 | - | in | IOB50[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R5/4 | - | in | IOB50[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R4/4 | - | in | IOB52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T3/4 | - | in | IOB52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R6/4 | - | in | IOB54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T5/4 | - | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
B14/7 | - | in | IOL2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A15/7 | - | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C12/7 | - | in | IOL7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B12/7 | - | in | IOL7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B13/7 | - | in | IOL8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A14/7 | - | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F10/7 | - | in | IOL11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B11/7 | - | in | IOL13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A12/7 | - | in | IOL13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A11/7 | - | in | IOL15[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C11/7 | - | in | IOL15[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D10/7 | - | in | IOL17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E10/7 | - | in | IOL17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D11/7 | - | in | IOL22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A9/7 | - | in | IOL27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C9/7 | - | in | IOL27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C8/6 | - | in | IOL29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A8/6 | - | in | IOL29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F9/6 | - | in | IOL31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E11/6 | - | in | IOL31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B9/6 | - | in | IOL33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A10/6 | - | in | IOL33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F8/6 | - | in | IOL35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D9/6 | - | in | IOL35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D8/6 | - | in | IOL38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E9/6 | - | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B7/6 | - | in | IOL40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C7/6 | - | in | IOL40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F7/6 | - | in | IOL45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E8/6 | - | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C4/6 | - | in | IOL47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B5/6 | - | in | IOL47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E6/6 | - | in | IOL53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D7/6 | - | in | IOL53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
T15/2 | - | in | IOR7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R14/2 | - | in | IOR7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P12/2 | - | in | IOR8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T13/2 | - | in | IOR8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R12/2 | - | in | IOR11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P13/2 | - | in | IOR11[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R11/2 | - | in | IOR17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T12/2 | - | in | IOR17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R13/2 | - | in | IOR20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T14/2 | - | in | IOR20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M10/2 | - | in | IOR22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N11/2 | - | in | IOR22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T11/2 | - | in | IOR24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P11/2 | - | in | IOR24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C6/2 | - | out | IOR25[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
B8/2 | - | in | IOR25[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A7/2 | - | in | IOR26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A6/2 | - | in | IOR26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N10/2 | - | in | IOR27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M11/2 | - | in | IOR27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T7/3 | - | in | IOR29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R8/3 | - | in | IOR29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M16/3 | - | in | IOR30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B16/3 | - | in | IOR30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C15/3 | - | in | IOR31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
B10/3 | - | in | IOR31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
A13/3 | - | in | IOR32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C13/3 | - | in | IOR32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P10/3 | - | in | IOR33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R10/3 | - | in | IOR33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M9/3 | - | in | IOR34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L10/3 | - | in | IOR34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R9/3 | - | in | IOR35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T10/3 | - | in | IOR35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M8/3 | - | in | IOR36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N9/3 | - | in | IOR36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T9/3 | - | in | IOR38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P9/3 | - | in | IOR38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C10/3 | - | in | IOR39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N8/3 | - | in | IOR40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L9/3 | - | in | IOR40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P8/3 | - | in | IOR42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T8/3 | - | in | IOR42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M6/3 | - | in | IOR44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L8/3 | - | in | IOR44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M7/3 | - | in | IOR47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N7/3 | - | in | IOR47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R7/3 | - | in | IOR49[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P7/3 | - | in | IOR49[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N6/3 | - | in | IOR51[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P6/3 | - | in | IOR53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
T6/3 | - | in | IOR53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
====================================================================================================================================================================================

941
gowin/seq_light_test/impl/pnr/seq_light_test.timing_paths Normal file
View File

@ -0,0 +1,941 @@
=====
SETUP
6.732
9.734
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_24_s0
9.734
=====
SETUP
6.732
9.734
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_25_s0
9.734
=====
SETUP
6.732
9.734
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_26_s0
9.734
=====
SETUP
6.732
9.734
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_27_s0
9.734
=====
SETUP
6.732
9.734
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_28_s0
9.734
=====
SETUP
6.732
9.734
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_29_s0
9.734
=====
SETUP
6.740
9.726
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_31_s0
9.726
=====
SETUP
6.740
9.726
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_30_s0
9.726
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_12_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_13_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_14_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_15_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_16_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_17_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_18_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_19_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_20_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_21_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_22_s0
9.543
=====
SETUP
6.923
9.543
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_23_s0
9.543
=====
SETUP
6.927
9.539
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_1_s0
9.539
=====
SETUP
6.927
9.539
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_2_s0
9.539
=====
SETUP
6.927
9.539
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_3_s0
9.539
=====
SETUP
6.927
9.539
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_4_s0
9.539
=====
SETUP
6.927
9.539
16.466
clock_ibuf
0.000
4.230
clkcnt_26_s0
6.501
6.733
n38_s108
6.890
7.460
n38_s100
7.632
8.187
n38_s96
8.600
9.170
clkcnt_5_s0
9.539
=====
HOLD
-4.449
0.234
4.684
n72_s2
0.002
0.234
newclk_s1
0.234
=====
HOLD
0.425
5.074
4.649
clock_ibuf
0.000
3.126
clkcnt_2_s0
4.638
4.840
n35_s
4.842
5.074
clkcnt_2_s0
5.074
=====
HOLD
0.425
5.074
4.649
clock_ibuf
0.000
3.126
clkcnt_6_s0
4.638
4.840
n31_s
4.842
5.074
clkcnt_6_s0
5.074
=====
HOLD
0.425
5.074
4.649
clock_ibuf
0.000
3.126
clkcnt_8_s0
4.638
4.840
n29_s
4.842
5.074
clkcnt_8_s0
5.074
=====
HOLD
0.425
5.074
4.649
clock_ibuf
0.000
3.126
clkcnt_14_s0
4.638
4.840
n23_s
4.842
5.074
clkcnt_14_s0
5.074
=====
HOLD
0.425
5.074
4.649
clock_ibuf
0.000
3.126
clkcnt_20_s0
4.638
4.840
n17_s
4.842
5.074
clkcnt_20_s0
5.074
=====
HOLD
0.425
5.074
4.649
clock_ibuf
0.000
3.126
clkcnt_24_s0
4.638
4.840
n13_s
4.842
5.074
clkcnt_24_s0
5.074
=====
HOLD
0.425
5.074
4.649
clock_ibuf
0.000
3.126
clkcnt_26_s0
4.638
4.840
n11_s
4.842
5.074
clkcnt_26_s0
5.074
=====
HOLD
0.425
5.074
4.649
clock_ibuf
0.000
3.126
clkcnt_30_s0
4.638
4.840
n7_s
4.842
5.074
clkcnt_30_s0
5.074
=====
HOLD
0.425
2.197
1.771
fsm_2_s0
1.760
1.962
n111_s0
1.965
2.197
fsm_2_s0
2.197
=====
HOLD
0.427
5.075
4.649
clock_ibuf
0.000
3.126
clkcnt_0_s0
4.638
4.840
n37_s2
4.843
5.075
clkcnt_0_s0
5.075
=====
HOLD
0.427
5.075
4.649
clock_ibuf
0.000
3.126
clkcnt_12_s0
4.638
4.840
n25_s
4.843
5.075
clkcnt_12_s0
5.075
=====
HOLD
0.427
5.075
4.649
clock_ibuf
0.000
3.126
clkcnt_18_s0
4.638
4.840
n19_s
4.843
5.075
clkcnt_18_s0
5.075
=====
HOLD
0.542
5.191
4.649
clock_ibuf
0.000
3.126
clkcnt_31_s0
4.638
4.839
n6_s
4.959
5.191
clkcnt_31_s0
5.191
=====
HOLD
0.542
5.191
4.649
clock_ibuf
0.000
3.126
clkcnt_11_s0
4.638
4.839
n26_s
4.959
5.191
clkcnt_11_s0
5.191
=====
HOLD
0.542
5.191
4.649
clock_ibuf
0.000
3.126
clkcnt_23_s0
4.638
4.839
n14_s
4.959
5.191
clkcnt_23_s0
5.191
=====
HOLD
0.546
5.194
4.649
clock_ibuf
0.000
3.126
clkcnt_3_s0
4.638
4.839
n34_s
4.962
5.194
clkcnt_3_s0
5.194
=====
HOLD
0.546
5.194
4.649
clock_ibuf
0.000
3.126
clkcnt_4_s0
4.638
4.839
n33_s
4.962
5.194
clkcnt_4_s0
5.194
=====
HOLD
0.546
5.194
4.649
clock_ibuf
0.000
3.126
clkcnt_9_s0
4.638
4.839
n28_s
4.962
5.194
clkcnt_9_s0
5.194
=====
HOLD
0.546
5.194
4.649
clock_ibuf
0.000
3.126
clkcnt_16_s0
4.638
4.839
n21_s
4.962
5.194
clkcnt_16_s0
5.194
=====
HOLD
0.546
5.194
4.649
clock_ibuf
0.000
3.126
clkcnt_21_s0
4.638
4.839
n16_s
4.962
5.194
clkcnt_21_s0
5.194
=====
HOLD
0.546
5.194
4.649
clock_ibuf
0.000
3.126
clkcnt_22_s0
4.638
4.839
n15_s
4.962
5.194
clkcnt_22_s0
5.194
=====
HOLD
0.546
5.194
4.649
clock_ibuf
0.000
3.126
clkcnt_27_s0
4.638
4.839
n10_s
4.962
5.194
clkcnt_27_s0
5.194
=====
HOLD
0.546
5.194
4.649
clock_ibuf
0.000
3.126
clkcnt_28_s0
4.638
4.839
n9_s
4.962
5.194
clkcnt_28_s0
5.194
=====
HOLD
0.546
5.194
4.649
clock_ibuf
0.000
3.126
clkcnt_29_s0
4.638
4.839
n8_s
4.962
5.194
clkcnt_29_s0
5.194

10
gowin/seq_light_test/impl/pnr/seq_light_test.tr.html Normal file
View File

@ -0,0 +1,10 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Timing Analysis Report</title>
</head>
<frameset cols="20%, 80%">
<frame src="seq_light_test_tr_cata.html" name="cataFrame" />
<frame src="seq_light_test_tr_content.html" name="mainFrame"/>
</frameset>
</html>

132
gowin/seq_light_test/impl/pnr/seq_light_test_tr_cata.html Normal file
View File

@ -0,0 +1,132 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Timing Report Navigation</title>
<style type="text/css">
@import url(../temp/style.css);
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#catalog_wrapper { width: 100%; }
div#catalog ul { list-style: none; margin-left: -15px; }
div#catalog ul li { margin: 3px 0 3px 0; text-align: left; color: #0084ff; white-space: nowrap; word-break: keep-all; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 4px; margin: 0 0 0 0; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
div.triangle_fake, div.triangle { display: inline-block; cursor: pointer; width: 8px; height: 0; border-top: 5px solid transparent; border-bottom: 5px solid transparent; }
div.triangle_fake { border-left: 5px solid transparent; }
div.triangle { border-left: 5px solid #0084ff; }
div.triangle:hover { border-left-color: #000; }
</style>
<script>
function onClick(obj){var childs=obj.parentNode.childNodes;for(var i=0;i<childs.length;i++){if(childs[i].tagName=="UL"){if(childs[i].style.display=="none"){childs[i].style.display="block"}else{childs[i].style.display="none"}}}};
</script>
</head>
<body>
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<!-- messages begin-->
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#Message" target="mainFrame" style=" font-size: 16px;">Timing Messages</a></li>
<!-- messages end-->
<!-- summaries begin-->
<li><div class="triangle" onclick="onClick(this)"></div><a href="seq_light_test_tr_content.html#Summary" style=" font-size: 16px;" target="mainFrame">Timing Summaries</a>
<ul>
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#STA_Tool_Run_Summary" style=" font-size: 14px;" target="mainFrame">STA Tool Run Summary</a></li>
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#Clock_Report" style=" font-size: 14px;" target="mainFrame">Clock Summary</a></li>
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#Max_Frequency_Report" style=" font-size: 14px;" target="mainFrame">Max Frequency Summary</a></li>
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#Total_Negative_Slack_Report" style=" font-size: 14px;" target="mainFrame">Total Negative Slack Summary</a></li>
</ul>
</li>
<!-- summaries end-->
<!-- details begin-->
<li><div class="triangle" onclick="onClick(this)"></div><a href="seq_light_test_tr_content.html#Detail" style=" font-size: 16px;" target="mainFrame">Timing Details</a>
<ul>
<!--All_Path_Slack_Table begin-->
<li><div class="triangle" onclick="onClick(this)"></div><a href="seq_light_test_tr_content.html#All_Path_Slack_Table" style=" font-size: 14px;" target="mainFrame">Path Slacks Table</a>
<ul>
<!--Setup_Slack_Table begin-->
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#Setup_Slack_Table" style=" font-size: 13px;" target="mainFrame">Setup Paths Table</a>
</li>
<!--Setup_Slack_Table end-->
<!--Hold_Slack_Table begin-->
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#Hold_Slack_Table" style=" font-size: 13px;color: #FF0000;" class = "error" target="mainFrame">Hold Paths Table</a>
</li>
<!--Hold_Slack_Table end-->
<!--Recovery_Slack_Table begin-->
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#Recovery_Slack_Table" style=" font-size: 13px;" target="mainFrame">Recovery Paths Table</a>
</li>
<!--Recovery_Slack_Table end-->
<!--Removal_Slack_Table begin-->
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#Removal_Slack_Table" style=" font-size: 13px;" target="mainFrame">Removal Paths Table</a>
</li>
<!--Removal_Slack_Table end-->
</ul>
</li><!--All_Path_Slack_Table end-->
<!--MIN_PULSE_WIDTH_TABLE begin-->
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#MIN_PULSE_WIDTH_TABLE" style=" font-size: 14px;" target="mainFrame">Minimum Pulse Width Table</a>
</li>
<!--MIN_PULSE_WIDTH_TABLE end-->
<!--Timing_Report_by_Analysis_Type begin-->
<li><div class="triangle" onclick="onClick(this)"></div><a href="seq_light_test_tr_content.html#Timing_Report_by_Analysis_Type" style=" font-size: 14px;" target="mainFrame">Timing Report By Analysis Type</a>
<ul>
<!--Setup_Analysis begin-->
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#Setup_Analysis" style=" font-size: 13px;" target="mainFrame">Setup Analysis Report</a>
</li>
<!--Setup_Analysis end-->
<!--Hold_Analysis begin-->
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#Hold_Analysis" style=" font-size: 13px;" target="mainFrame">Hold Analysis Report</a>
</li>
<!--Hold_Analysis end-->
<!--Recovery_Analysis begin-->
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#Recovery_Analysis" style=" font-size: 13px;" target="mainFrame">Recovery Analysis Report</a>
</li>
<!--Recovery_Analysis end-->
<!--Removal_Analysis begin-->
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#Removal_Analysis" style=" font-size: 13px;" target="mainFrame">Removal Analysis Report</a>
</li>
<!--Removal_Analysis end-->
</ul>
</li>
<!--Timing_Report_by_Analysis_Type end-->
<!--Minimum_Pulse_Width_Report begin-->
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#Minimum_Pulse_Width_Report" style=" font-size: 14px;" target="mainFrame">Minimum Pulse Width Report</a>
</li>
<!--Minimum_Pulse_Width_Report end-->
<!--High_Fanout_Nets_Report begin-->
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#High_Fanout_Nets_Report" style=" font-size: 14px;" target="mainFrame">High Fanout Nets Report</a></li>
<!--High_Fanout_Nets_Report end-->
<!--Route_Congestions_Report begin-->
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#Route_Congestions_Report" style=" font-size: 14px;" target="mainFrame">Route Congestions Report</a></li>
<!--Route_Congestions_Report end-->
<!--Timing_Exceptions_Report begin-->
<li><div class="triangle" onclick="onClick(this)"></div><a href="seq_light_test_tr_content.html#Timing_Exceptions_Report" style=" font-size: 14px;" target="mainFrame">Timing Exceptions Report</a>
<ul>
<!--Setup_Analysis_Exceptions begin-->
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#Setup_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Setup Analysis Report</a>
</li>
<!--Setup_Analysis_Exceptions end-->
<!--Hold_Analysis_Exceptions begin-->
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#Hold_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Hold Analysis Report</a>
</li>
<!--Hold_Analysis_Exceptions end-->
<!--Recovery_Analysis_Exceptions begin-->
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#Recovery_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Recovery Analysis Report</a>
</li>
<!--Recovery_Analysis_Exceptions end-->
<!--Removal_Analysis_Exceptions begin-->
<li><div class="triangle_fake" onclick="onClick(this)"></div><a href="seq_light_test_tr_content.html#Removal_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Removal Analysis Report</a>
</li>
<!--Removal_Analysis_Exceptions end-->
</ul>
</li>
<!--Timing_Exceptions_Report end-->
<!--SDC_Report begin-->
<li><div class="triangle_fake"></div><a href="seq_light_test_tr_content.html#SDC_Report" style=" font-size: 14px;" target="mainFrame">Timing Constraints Report</a></li>
<!--SDC_Report end-->
</ul>
</li>
<!-- details end-->
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
</body>
</html>

13983
gowin/seq_light_test/impl/pnr/seq_light_test_tr_content.html Normal file
View File

File diff suppressed because it is too large Load Diff

88
gowin/seq_light_test/impl/seq_light_test_process_config.json Normal file
View File

@ -0,0 +1,88 @@
{
"BACKGROUND_PROGRAMMING" : "off",
"COMPRESS" : false,
"CPU" : false,
"CRC_CHECK" : true,
"Clock_Route_Order" : 0,
"Correct_Hold_Violation" : true,
"DONE" : false,
"DOWNLOAD_SPEED" : "default",
"Disable_Insert_Pad" : false,
"ENABLE_CTP" : false,
"ENABLE_MERGE_MODE" : false,
"ENCRYPTION_KEY" : false,
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
"ERROR_DECTION_AND_CORRECTION" : false,
"ERROR_DECTION_ONLY" : false,
"ERROR_INJECTION" : false,
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
"Enable_DSRM" : false,
"FORMAT" : "binary",
"FREQUENCY_DIVIDER" : "",
"Generate_Constraint_File_of_Ports" : false,
"Generate_IBIS_File" : false,
"Generate_Plain_Text_Timing_Report" : false,
"Generate_Post_PNR_Simulation_Model_File" : false,
"Generate_Post_Place_File" : false,
"Generate_SDF_File" : false,
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
"Global_Freq" : "default",
"GwSyn_Loop_Limit" : 2000,
"HOTBOOT" : false,
"I2C" : false,
"I2C_SLAVE_ADDR" : "00",
"IncludePath" : [
],
"Incremental_Compile" : "",
"Initialize_Primitives" : false,
"JTAG" : false,
"MODE_IO" : false,
"MSPI" : false,
"MSPI_JUMP" : false,
"MULTIBOOT_ADDRESS_WIDTH" : "24",
"MULTIBOOT_MODE" : "Normal",
"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
"MULTIJUMP_ADDRESS_WIDTH" : "24",
"MULTIJUMP_MODE" : "Normal",
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
"Multi_Boot" : true,
"OUTPUT_BASE_NAME" : "seq_light_test",
"POWER_ON_RESET_MONITOR" : true,
"PRINT_BSRAM_VALUE" : true,
"PROGRAM_DONE_BYPASS" : false,
"PlaceInRegToIob" : true,
"PlaceIoRegToIob" : true,
"PlaceOutRegToIob" : true,
"Place_Option" : "0",
"Process_Configuration_Verion" : "1.0",
"Promote_Physical_Constraint_Warning_to_Error" : true,
"READY" : false,
"RECONFIG_N" : false,
"Ram_RW_Check" : false,
"Replicate_Resources" : false,
"Report_Auto-Placed_Io_Information" : false,
"Route_Maxfan" : 23,
"Route_Option" : "0",
"Run_Timing_Driven" : true,
"SECURE_MODE" : false,
"SECURITY_BIT" : true,
"SEU_HANDLER" : false,
"SEU_HANDLER_CHECKSUM" : false,
"SEU_HANDLER_MODE" : "auto",
"SSPI" : false,
"STOP_SEU_HANDLER" : false,
"Show_All_Warnings" : false,
"Synthesize_tool" : "GowinSyn",
"TclPre" : "",
"TopModule" : "",
"USERCODE" : "default",
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
"VCCAUX" : 3.3,
"VCCX" : "3.3",
"VHDL_Standard" : "VHDL_Std_1993",
"Verilog_Standard" : "Vlg_Std_2001",
"WAKE_UP" : "0",
"show_all_warnings" : false,
"turn_off_bg" : false
}

10
gowin/seq_light_test/impl/temp/rtl_parser.result Normal file
View File

@ -0,0 +1,10 @@
[
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/src/seqBlink.v",
"InstLine" : 1,
"InstName" : "seqBlink",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/src/seqBlink.v",
"ModuleLine" : 1,
"ModuleName" : "seqBlink"
}
]

17
gowin/seq_light_test/impl/temp/rtl_parser_arg.json Normal file
View File

@ -0,0 +1,17 @@
{
"Device" : "GW2A-18C",
"Files" : [
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/src/seqBlink.v",
"Type" : "verilog"
}
],
"IncludePath" : [
],
"LoopLimit" : 2000,
"ResultFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/seq_light_test/impl/temp/rtl_parser.result",
"Top" : "",
"VerilogStd" : "verilog_2001",
"VhdlStd" : "vhdl_93"
}

0
gowin/seq_light_test/impl/temp/style.css Normal file
View File

12
gowin/seq_light_test/seq_light_test.gprj Normal file
View File

@ -0,0 +1,12 @@
<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
<FileList>
<File path="src/seqBlink.v" type="file.verilog" enable="1"/>
<File path="src/seqBlinkTB.v" type="file.verilog" enable="0"/>
<File path="src/seq_light_test.cst" type="file.cst" enable="1"/>
</FileList>
</Project>

24
gowin/seq_light_test/seq_light_test.gprj.user Normal file
View File

@ -0,0 +1,24 @@
<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE ProjectUserData>
<UserConfig>
<Version>1.0</Version>
<FlowState>
<Process ID="Synthesis" State="2"/>
<Process ID="Pnr" State="2"/>
<Process ID="Gao" State="2"/>
<Process ID="Rtl_Gao" State="2"/>
</FlowState>
<ResultFileList>
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/seq_light_test.vg"/>
<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/seq_light_test.fs"/>
<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/seq_light_test.pin.html"/>
<ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/seq_light_test.db"/>
<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/seq_light_test.power.html"/>
<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/seq_light_test.rpt.html"/>
<ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/seq_light_test.timing_paths"/>
<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/seq_light_test.tr.html"/>
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/seq_light_test_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/seq_light_test_syn_rsc.xml"/>
</ResultFileList>
<Ui>000000ff00000001fd00000002000000000000018e00000260fc0200000001fc00000063000002600000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000078000000142fc0100000001fc00000000000007800000009b00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000007800fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000009b00ffffff000005ea0000026000000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000afffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000183ffffffff0000000000000000</Ui>
</UserConfig>

36
gowin/seq_light_test/src/seqBlink.v Normal file
View File

@ -0,0 +1,36 @@
module seqBlink (
input clock,
output reg [3:0] led
);
reg [2:0] fsm = 0;
reg [31:0] clkcnt = 0;
reg newclk = 0;
always@(posedge clock) begin
clkcnt <= clkcnt + 1'b1;
if (clkcnt > 9_000_000) begin
clkcnt <= 0;
newclk <= ~newclk;
end
end
always@(posedge newclk) begin
if (fsm == 3'd6) begin
fsm <= 0;
end else begin
fsm <= fsm + 1;
end
case (fsm)
3'b000 : led <= 4'b0111;
3'b001 : led <= 4'b1011;
3'b010 : led <= 4'b1101;
3'b011 : led <= 4'b1110;
3'b100 : led <= 4'b1101;
3'b101 : led <= 4'b1011;
3'b110 : led <= 4'b0111;
default: led <= 4'b0000;
endcase
end
endmodule

24
gowin/seq_light_test/src/seqBlinkTB.v Normal file
View File

@ -0,0 +1,24 @@
module seqBlinkTB();
reg clock;
wire [3:0] leds;
seqBlink uut(clock, leds);
initial begin
clock = 0;
end
always begin
clock = ~clock; #5;
end
initial begin
$dumpfile("lab5v.vcd");
$dumpvars;
#100;
$finish;
end
endmodule

19
gowin/seq_light_test/src/seq_light_test.cst Normal file
View File

@ -0,0 +1,19 @@
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Physical Constraints file
//Tool Version: V1.9.9.03 Education (64-bit)
//Part Number: GW2A-LV18PG256C8/I7
//Device: GW2A-18
//Device Version: C
//Created Time: Sun 07 07 15:26:30 2024
IO_LOC "led[3]" L16;
IO_PORT "led[3]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "led[2]" L14;
IO_PORT "led[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "led[1]" N14;
IO_PORT "led[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "led[0]" N16;
IO_PORT "led[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "clock" H11;
IO_PORT "clock" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;

68
labs/lab5/lab5 Normal file
View File

@ -0,0 +1,68 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55ec01128cc0 .scope module, "seqBlinkTB" "seqBlinkTB" 2 1;
.timescale 0 0;
v0x55ec01139850_0 .var "clock", 0 0;
v0x55ec01139920_0 .net "leds", 3 0, v0x55ec01139650_0; 1 drivers
S_0x55ec01128e50 .scope module, "uut" "seqBlink" 2 6, 3 1 0, S_0x55ec01128cc0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clock";
.port_info 1 /OUTPUT 4 "leds";
v0x55ec010f07f0_0 .net "clock", 0 0, v0x55ec01139850_0; 1 drivers
v0x55ec010f0c00_0 .var "count", 1 0;
v0x55ec01139650_0 .var "leds", 3 0;
v0x55ec01139710_0 .var "start", 3 0;
E_0x55ec01127bc0 .event posedge, v0x55ec010f07f0_0;
.scope S_0x55ec01128e50;
T_0 ;
%pushi/vec4 0, 0, 2;
%store/vec4 v0x55ec010f0c00_0, 0, 2;
%pushi/vec4 1, 0, 4;
%store/vec4 v0x55ec01139710_0, 0, 4;
%end;
.thread T_0;
.scope S_0x55ec01128e50;
T_1 ;
%wait E_0x55ec01127bc0;
%load/vec4 v0x55ec010f0c00_0;
%addi 1, 0, 2;
%assign/vec4 v0x55ec010f0c00_0, 0;
%load/vec4 v0x55ec01139710_0;
%ix/getv 4, v0x55ec010f0c00_0;
%shiftl 4;
%assign/vec4 v0x55ec01139650_0, 0;
%jmp T_1;
.thread T_1;
.scope S_0x55ec01128cc0;
T_2 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55ec01139850_0, 0, 1;
T_2.0 ;
%delay 5, 0;
%load/vec4 v0x55ec01139850_0;
%inv;
%store/vec4 v0x55ec01139850_0, 0, 1;
%jmp T_2.0;
%end;
.thread T_2;
.scope S_0x55ec01128cc0;
T_3 ;
%vpi_call 2 16 "$dumpfile", "lab5v.vcd" {0 0 0};
%vpi_call 2 17 "$dumpvars" {0 0 0};
%delay 100, 0;
%vpi_call 2 21 "$finish" {0 0 0};
%end;
.thread T_3;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"seqBlinkTB.v";
"seqBlink.v";

98
labs/lab5/lab5v.vcd Normal file
View File

@ -0,0 +1,98 @@
$date
Sun Jul 7 02:46:47 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module seqBlinkTB $end
$var wire 4 ! leds [3:0] $end
$var reg 1 " clock $end
$scope module uut $end
$var wire 1 " clock $end
$var reg 2 # count [1:0] $end
$var reg 4 $ leds [3:0] $end
$var reg 4 % start [3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b1 %
bx $
b0 #
0"
bx !
$end
#5
b1 !
b1 $
b1 #
1"
#10
0"
#15
b10 !
b10 $
b10 #
1"
#20
0"
#25
b100 !
b100 $
b11 #
1"
#30
0"
#35
b1000 !
b1000 $
b0 #
1"
#40
0"
#45
b1 !
b1 $
b1 #
1"
#50
0"
#55
b10 !
b10 $
b10 #
1"
#60
0"
#65
b100 !
b100 $
b11 #
1"
#70
0"
#75
b1000 !
b1000 $
b0 #
1"
#80
0"
#85
b1 !
b1 $
b1 #
1"
#90
0"
#95
b10 !
b10 $
b10 #
1"
#100
0"

36
labs/lab5/seqBlink.v Normal file
View File

@ -0,0 +1,36 @@
module seqBlink (
input clock,
output reg [3:0] led
);
reg [2:0] fsm = 0;
reg [31:0] clkcnt = 0;
reg newclk = 0;
always@(posedge clock) begin
clkcnt <= clkcnt + 1'b1;
if (clkcnt > 9_000_000) begin
clkcnt <= 0;
newclk <= ~newclk;
end
end
always@(posedge newclk) begin
if (fsm == 3'd7) begin
fsm <= 0;
end else begin
fsm <= fsm + 1;
end
case (fsm)
3'b000 : led <= 4'b0111;
3'b001 : led <= 4'b1011;
3'b010 : led <= 4'b1101;
3'b011 : led <= 4'b1110;
3'b100 : led <= 4'b1101;
3'b101 : led <= 4'b1011;
3'b110 : led <= 4'b0111;
default: led <= 4'b0000;
endcase
end
endmodule

24
labs/lab5/seqBlinkTB.v Normal file
View File

@ -0,0 +1,24 @@
module seqBlinkTB();
reg clock;
wire [3:0] leds;
seqBlink uut(clock, leds);
initial begin
clock = 0;
forever begin
#5 clock = ~clock;
end
end
initial begin
$dumpfile("lab5v.vcd");
$dumpvars;
#100;
$finish;
end
endmodule