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verilog

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k0rrluna
2024-07-07 15:51:02 +03:00
parent c1f0851a45
commit 339ae1f428
35 changed files with 26577 additions and 1 deletions
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68
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#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55ec01128cc0 .scope module, "seqBlinkTB" "seqBlinkTB" 2 1;
.timescale 0 0;
v0x55ec01139850_0 .var "clock", 0 0;
v0x55ec01139920_0 .net "leds", 3 0, v0x55ec01139650_0; 1 drivers
S_0x55ec01128e50 .scope module, "uut" "seqBlink" 2 6, 3 1 0, S_0x55ec01128cc0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clock";
.port_info 1 /OUTPUT 4 "leds";
v0x55ec010f07f0_0 .net "clock", 0 0, v0x55ec01139850_0; 1 drivers
v0x55ec010f0c00_0 .var "count", 1 0;
v0x55ec01139650_0 .var "leds", 3 0;
v0x55ec01139710_0 .var "start", 3 0;
E_0x55ec01127bc0 .event posedge, v0x55ec010f07f0_0;
.scope S_0x55ec01128e50;
T_0 ;
%pushi/vec4 0, 0, 2;
%store/vec4 v0x55ec010f0c00_0, 0, 2;
%pushi/vec4 1, 0, 4;
%store/vec4 v0x55ec01139710_0, 0, 4;
%end;
.thread T_0;
.scope S_0x55ec01128e50;
T_1 ;
%wait E_0x55ec01127bc0;
%load/vec4 v0x55ec010f0c00_0;
%addi 1, 0, 2;
%assign/vec4 v0x55ec010f0c00_0, 0;
%load/vec4 v0x55ec01139710_0;
%ix/getv 4, v0x55ec010f0c00_0;
%shiftl 4;
%assign/vec4 v0x55ec01139650_0, 0;
%jmp T_1;
.thread T_1;
.scope S_0x55ec01128cc0;
T_2 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55ec01139850_0, 0, 1;
T_2.0 ;
%delay 5, 0;
%load/vec4 v0x55ec01139850_0;
%inv;
%store/vec4 v0x55ec01139850_0, 0, 1;
%jmp T_2.0;
%end;
.thread T_2;
.scope S_0x55ec01128cc0;
T_3 ;
%vpi_call 2 16 "$dumpfile", "lab5v.vcd" {0 0 0};
%vpi_call 2 17 "$dumpvars" {0 0 0};
%delay 100, 0;
%vpi_call 2 21 "$finish" {0 0 0};
%end;
.thread T_3;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"seqBlinkTB.v";
"seqBlink.v";

98
labs/lab5/lab5v.vcd Normal file
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$date
Sun Jul 7 02:46:47 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module seqBlinkTB $end
$var wire 4 ! leds [3:0] $end
$var reg 1 " clock $end
$scope module uut $end
$var wire 1 " clock $end
$var reg 2 # count [1:0] $end
$var reg 4 $ leds [3:0] $end
$var reg 4 % start [3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b1 %
bx $
b0 #
0"
bx !
$end
#5
b1 !
b1 $
b1 #
1"
#10
0"
#15
b10 !
b10 $
b10 #
1"
#20
0"
#25
b100 !
b100 $
b11 #
1"
#30
0"
#35
b1000 !
b1000 $
b0 #
1"
#40
0"
#45
b1 !
b1 $
b1 #
1"
#50
0"
#55
b10 !
b10 $
b10 #
1"
#60
0"
#65
b100 !
b100 $
b11 #
1"
#70
0"
#75
b1000 !
b1000 $
b0 #
1"
#80
0"
#85
b1 !
b1 $
b1 #
1"
#90
0"
#95
b10 !
b10 $
b10 #
1"
#100
0"

36
labs/lab5/seqBlink.v Normal file
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module seqBlink (
input clock,
output reg [3:0] led
);
reg [2:0] fsm = 0;
reg [31:0] clkcnt = 0;
reg newclk = 0;
always@(posedge clock) begin
clkcnt <= clkcnt + 1'b1;
if (clkcnt > 9_000_000) begin
clkcnt <= 0;
newclk <= ~newclk;
end
end
always@(posedge newclk) begin
if (fsm == 3'd7) begin
fsm <= 0;
end else begin
fsm <= fsm + 1;
end
case (fsm)
3'b000 : led <= 4'b0111;
3'b001 : led <= 4'b1011;
3'b010 : led <= 4'b1101;
3'b011 : led <= 4'b1110;
3'b100 : led <= 4'b1101;
3'b101 : led <= 4'b1011;
3'b110 : led <= 4'b0111;
default: led <= 4'b0000;
endcase
end
endmodule

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labs/lab5/seqBlinkTB.v Normal file
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module seqBlinkTB();
reg clock;
wire [3:0] leds;
seqBlink uut(clock, leds);
initial begin
clock = 0;
forever begin
#5 clock = ~clock;
end
end
initial begin
$dumpfile("lab5v.vcd");
$dumpvars;
#100;
$finish;
end
endmodule