kaltinsoy/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

bttnTB

Browse Source
This commit is contained in:
k0rrluna 2025-01-20 15:16:37 +03:00
parent a007343feb
commit 15916a2c53
48 changed files with 8567 additions and 4186 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
gowin/bttn/bttn.gprj.user
View File

@ -7,6 +7,8 @@
<Process ID="Pnr" State="2"/>
<Process ID="Gao" State="2"/>
<Process ID="Rtl_Gao" State="2"/>
<Process ID="Gvio" State="2"/>
<Process ID="Place" State="2"/>
</FlowState>
<ResultFileList>
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/bttn.vg"/>
@ -20,5 +22,6 @@
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/bttn_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/bttn_syn_rsc.xml"/>
</ResultFileList>
<Ui>000000ff00000001fd00000002000000000000018e0000051efc0200000001fc000000630000051e0000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff00000000000000000000000300000ab000000145fc0100000001fc0000000000000ab0000000e700fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000009e00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000e700ffffff0000091a0000051e00000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000bdffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c007301000001a5ffffffff0000000000000000</Ui>
<Ui>000000ff00000001fd00000002000000000000018e0000025dfc0200000001fc000000370000025d0000000000fffffffaffffffff0200000004fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000000000030000078000000145fc0100000001fc00000000000007800000009b00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000009b00ffffff000005ee0000025d00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000adffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c0073010000017fffffffff0000000000000000000000280043006f00720065002e0054006f006f006c006200610072002e00500072006f00630065007300730100000245ffffffff0000000000000000</Ui>
<FpUi></FpUi>
</UserConfig>

6
gowin/bttn/impl/bttn_process_config.json
View File

@ -4,6 +4,7 @@
"CPU" : false,
"CRC_CHECK" : true,
"Clock_Route_Order" : 0,
"Convert_SDP32_36_to_SDP16_18" : true,
"Correct_Hold_Violation" : true,
"DONE" : false,
"DOWNLOAD_SPEED" : "default",
@ -18,7 +19,7 @@
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
"Enable_DSRM" : false,
"FORMAT" : "binary",
"FREQUENCY_DIVIDER" : "",
"FREQUENCY_DIVIDER" : "1",
"Generate_Constraint_File_of_Ports" : false,
"Generate_IBIS_File" : false,
"Generate_Plain_Text_Timing_Report" : false,
@ -31,6 +32,8 @@
"HOTBOOT" : false,
"I2C" : false,
"I2C_SLAVE_ADDR" : "00",
"INCREMENTAL_PLACE_AND_ROUTING" : "0",
"INCREMENTAL_PLACE_ONLY" : "0",
"IncludePath" : [
],
@ -78,6 +81,7 @@
"TopModule" : "",
"USERCODE" : "default",
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
"VCC" : "1.0",
"VCCAUX" : 3.3,
"VCCX" : "3.3",
"VHDL_Standard" : "VHDL_Std_1993",

320
gowin/bttn/impl/temp/rtl_parser.result
View File

@ -1,143 +1,143 @@
[
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/bttn.v",
"InstLine" : 1,
"InstName" : "bttn",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/bttn.v",
"ModuleLine" : 1,
"ModuleName" : "bttn",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/bttn.v",
"InstLine" : 10,
"InstName" : "a1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
"ModuleLine" : 1,
"ModuleName" : "ALU",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
"InstLine" : 18,
"InstName" : "opCd",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/opCode.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/opCode.v",
"ModuleLine" : 1,
"ModuleName" : "opCode"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
"InstLine" : 20,
"InstName" : "aU",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
"ModuleLine" : 1,
"ModuleName" : "arithmeticUnit",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
"InstLine" : 13,
"InstName" : "a1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"ModuleLine" : 1,
"ModuleName" : "addition",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 11,
"InstName" : "f0",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 12,
"InstName" : "f1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 13,
"InstName" : "f2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 14,
"InstName" : "f3",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
@ -146,112 +146,112 @@
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
"InstLine" : 14,
"InstName" : "s1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/subtraction.v",
"ModuleLine" : 1,
"ModuleName" : "subtraction",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/subtraction.v",
"InstLine" : 11,
"InstName" : "f0",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "fullsubtraction",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 8,
"InstName" : "hf1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 9,
"InstName" : "hf2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/subtraction.v",
"InstLine" : 12,
"InstName" : "f1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "fullsubtraction",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 8,
"InstName" : "hf1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 9,
"InstName" : "hf2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/subtraction.v",
"InstLine" : 13,
"InstName" : "f2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "fullsubtraction",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 8,
"InstName" : "hf1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 9,
"InstName" : "hf2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/subtraction.v",
"InstLine" : 14,
"InstName" : "f3",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "fullsubtraction",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 8,
"InstName" : "hf1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"InstLine" : 9,
"InstName" : "hf2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"ModuleLine" : 1,
"ModuleName" : "halfsubtraction"
}
@ -262,128 +262,128 @@
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
"InstLine" : 21,
"InstName" : "lU",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/logicUnit.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/logicUnit.v",
"ModuleLine" : 1,
"ModuleName" : "logicUnit"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
"InstLine" : 22,
"InstName" : "mU",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/multiplier.v",
"ModuleLine" : 1,
"ModuleName" : "multiplier",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/multiplier.v",
"InstLine" : 26,
"InstName" : "add0",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"ModuleLine" : 1,
"ModuleName" : "addition",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 11,
"InstName" : "f0",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 12,
"InstName" : "f1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 13,
"InstName" : "f2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 14,
"InstName" : "f3",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
@ -392,112 +392,112 @@
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/multiplier.v",
"InstLine" : 42,
"InstName" : "add1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"ModuleLine" : 1,
"ModuleName" : "addition",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 11,
"InstName" : "f0",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 12,
"InstName" : "f1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 13,
"InstName" : "f2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 14,
"InstName" : "f3",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
@ -506,112 +506,112 @@
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/multiplier.v",
"InstLine" : 58,
"InstName" : "add2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"ModuleLine" : 1,
"ModuleName" : "addition",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 11,
"InstName" : "f0",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 12,
"InstName" : "f1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 13,
"InstName" : "f2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"InstLine" : 14,
"InstName" : "f3",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"ModuleLine" : 1,
"ModuleName" : "fulladder",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 8,
"InstName" : "h1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"InstLine" : 9,
"InstName" : "h2",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"ModuleLine" : 1,
"ModuleName" : "halfadder"
}
@ -622,66 +622,66 @@
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
"InstLine" : 76,
"InstName" : "btod1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"ModuleLine" : 1,
"ModuleName" : "BinaryToBCD",
"SubInsts" : [
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 14,
"InstName" : "d1t",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 23,
"InstName" : "d2u",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 32,
"InstName" : "d3v",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 41,
"InstName" : "d4w",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 50,
"InstName" : "d5x",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 59,
"InstName" : "d6y",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"InstLine" : 68,
"InstName" : "d7z",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"ModuleLine" : 1,
"ModuleName" : "dabble"
}
@ -690,10 +690,10 @@
]
},
{
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/bttn.v",
"InstLine" : 11,
"InstName" : "s1",
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/selector.v",
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/selector.v",
"ModuleLine" : 1,
"ModuleName" : "selector"
}

32
gowin/bttn/impl/temp/rtl_parser_arg.json
View File

@ -2,63 +2,63 @@
"Device" : "GW2A-18C",
"Files" : [
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/bttn.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/logicUnit.v",
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/logicUnit.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v",
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/multiplier.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/opCode.v",
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/opCode.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/selector.v",
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/selector.v",
"Type" : "verilog"
},
{
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/subtraction.v",
"Type" : "verilog"
}
],
@ -66,7 +66,7 @@
],
"LoopLimit" : 2000,
"ResultFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/impl/temp/rtl_parser.result",
"ResultFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/impl/temp/rtl_parser.result",
"Top" : "",
"VerilogStd" : "verilog_2001",
"VhdlStd" : "vhdl_93"

2109
spartanTest/ALU
View File

File diff suppressed because it is too large Load Diff

1074
spartanTest/ALU.vcd
View File

File diff suppressed because it is too large Load Diff

42
spartanTest/ALUTB.v
View File

@ -1,42 +0,0 @@
module ALUTB ();
reg [3:0] A, B;
reg CarryIN;
reg [2:0] opCodeA;
wire CarryOUT, overflow;
wire [11:0] bcd;
ALU uut(
.A(A),
.B(B),
.CarryIN(CarryIN),
.opCodeA(opCodeA),
.CarryOUT(CarryOUT),
.bcd(bcd),
.overflow(overflow)
);
initial begin
$dumpfile("ALU.vcd"); // GTKWAVE SIMULTAIN DATA WAVEFORM
$dumpvars; // ICARUS VERILOG ADD ALL VARIABLES
A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b011; #5;
A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b011; #5;
A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b011; #5;
A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b011; #5;
A = 4'b0111; B = 4'b0111; CarryIN = 1'b1; opCodeA = 3'b011; #5;
A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b111; #5;
A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b111; #5;
A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b111; #5;
A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b111; #5;
A = 4'b0111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b111; #5;
A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b010; #5;
A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b010; #5;
A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b010; #5;
A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b010; #5;
A = 4'b0111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b010; #5;
$finish; //NOT CONTAIN CLK, BUT STILL STOPS CODE
end
endmodule

26
spartanTest/ALUtb.v
View File

@ -1,26 +0,0 @@
module ALUtb ();
reg [3:0] A, B;
reg CarryIN;
reg [2:0] opCodeA;
wire [11:0] bcd;
wire CarryOUT, overflow;
ALU uut (
.A(A),
.B(B),
.CarryIN(CarryIN),
.opCodeA(opCodeA),
.bcd(bcd),
.CarryOUT(CarryOUT),
.overflow(overflow)
);
initial begin
$dumpfile("ALU.vcd");
$dumpvars;
A = 4'b1100; B = 4'b1100; CarryIN = 1'b0; opCodeA = 3'b010; #5;
$finish;
end
endmodule

40
spartanTest/BinaryToBCDTB.v
View File

@ -1,40 +0,0 @@
module BinaryToBCDTB;
// Testbench signals
reg [7:0] binary;
wire [11:0] bcd; // Output BCD
// Instantiate the BinaryToBCD module
BinaryToBCD uut (
.binary(binary),
.bcd(bcd)
);
// Testbench procedure
initial begin
$monitor("Time: %0t | Binary: %b | BCD: %b (Hundreds: %d, Tens: %d, Ones: %d)",
$time, binary, bcd, bcd[11:8], bcd[7:4], bcd[3:0]);
$dumpfile("BinaryToBCD.vcd");
$dumpvars;
// Test cases
binary = 8'b00000000; // Decimal: 0
#10;
binary = 8'b00001010; // Decimal: 10
#10;
binary = 8'b00101010; // Decimal: 42
#10;
binary = 8'b01100011; // Decimal: 99
#10;
binary = 8'b10011001; // Decimal: 153
#10;
binary = 8'b11111111; // Decimal: 255
#10;
// End simulation
$finish;
end
endmodule

41
spartanTest/char_mem.v
View File

@ -1,41 +0,0 @@
module char_mem (
input [4:0] addr,
output [7:0] bus,
input [3:0] A,
input [3:0] B,
input [2:0] opCode,
input [7:0] Y
);
parameter LINES = 2;
parameter CHARS_PER_LINE = 16;
parameter BITS_PER_CHAR = 8;
parameter STR_SIZE = LINES * CHARS_PER_LINE * BITS_PER_CHAR;
// Map the data into strings for display
wire [127:0] line1 = { "A:", nibble_to_ascii(A), " B:", nibble_to_ascii(B), " " };
wire [127:0] line2 = { "op:", nibble_to_ascii({1'b0, opCode}), " Y:", byte_to_ascii(Y) };
// Combine the two lines
wire [0:STR_SIZE-1] display_data = { line1, line2 };
// Address selection for the LCD
assign bus = display_data[{addr[4:0], 3'b000}+:8];
// Converts a 4-bit nibble to two ASCII characters
function [15:0] nibble_to_ascii;
input [3:0] nibble;
begin
nibble_to_ascii[15:8] = (nibble[3:0] >= 4'd10) ? (nibble[3:0] - 4'd10 + "A") : (nibble[3:0] + "0");
nibble_to_ascii[7:0] = " ";
end
endfunction
// Converts an 8-bit byte to two ASCII characters
function [15:0] byte_to_ascii;
input [7:0] byte;
begin
byte_to_ascii[15:8] = ((byte >> 4) >= 4'd10) ? ((byte >> 4) - 4'd10 + "A") : ((byte >> 4) + "0");
byte_to_ascii[7:0] = ((byte & 4'hF) >= 4'd10) ? ((byte & 4'hF) - 4'd10 + "A") : ((byte & 4'hF) + "0");
end
endfunction
endmodule

105
spartanTest/data.jed
View File

@ -1,105 +0,0 @@
JEDEC Programming File for /home/ise/ise/data.jed
Date: Sat Oct 26 08:09:00 2024
QF25812*
QP0*
F0*
X0*
N DEVICE xc2c64a-XXXXX*
L000000 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L000274 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L000548 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L000822 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L001096 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L001370 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L001644 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L001918 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L002192 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L002466 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L002740 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L003014 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L003288 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L003562 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L003836 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004110 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004384 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004658 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004932 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L005206 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L005480 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L005754 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000001111001*
L006028 1111100111111000000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111*
L006302 1001111110000000111100111111001111110000000111100111111001111110000000111100111111001111110000000111100111111001111110000000111100111111001111110011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110101101111111111111111111*
L006576 1111111111111111111111111111111111111110110101111111111111111111111111101101011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L006850 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L007124 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L007398 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L007672 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L007946 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L008220 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L008494 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L008768 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009042 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009316 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009590 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009864 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010138 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010412 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110111111101110111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010686 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010960 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L011234 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L011508 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L011782 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L012056 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L012330 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000111100111111001111110000000111100001110001111110000000111100111111001111110000000111100111111001111110000000111100111111001111110000000*
L012604 1111001111110011111100000001111001111110011111100000001111001111110011111100000001111001111110011111100000001111001111110011111100000001111001111110011111100000001111001111100110000001000001111001111110011111100000001111001111110011111100000001111001111110011111100000001111*
L012878 0011111100111111001111111111111111111111111111111111111111111111111111111111111111111111101111010111111111111111111111111010110111111111111111111111001110111111111111111111111111111111101101011111111111111111111111111011010111111111111111111111111111111111111111111111111111*
L013152 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L013426 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L013700 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L013974 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111101110111111011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L014248 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L014522 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L014796 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015070 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015344 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110111011111101111011111111111111111111111111111111111111111111111111111111*
L015618 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015892 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016166 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016440 1111111111111111111111111111111111111111111111111111111111111111111111110111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016714 1111111111111111111111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016988 1111011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017262 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110111111111111111111111111111111111111111111111111111111111111111*
L017536 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017810 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L018084 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L018358 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L018632 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L018906 1111110000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011001001110001010000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111010110001*
L019180 0100000111100111110101100010100000111100111110101100010100000111100111111001111110000000111100111110101100010100000111100111111001111110000000111100111111001111110011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L019454 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L019728 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020002 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020276 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020550 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020824 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021098 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021372 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021646 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021920 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022194 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022468 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022742 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023016 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023290 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023564 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023838 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L024112 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L024386 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L024660 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L024934 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
L025208 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000111100001110001111110000000111100001110001111110000000111100111111001111110000000111100111111001111110000000111100111*
L025482 1110011111100000001111001111110011111100000001111000011100011111100000001111001111110011111100000001111001111110011111100000001111001111110011111100000001111001111110011111100000001111001111110011111100000001111001111110011111100000001111001111110011111100000001111001111110*
L025756 01111110000000111100111111001111110000000111111110111111*
C2A9A*
0296

53
spartanTest/lcd.v
View File

@ -1,53 +0,0 @@
module lcd (
input clk,
output reg lcd_rs,
output reg lcd_rw,
output reg lcd_e,
output reg [7:4] lcd_d,
output [4:0] mem_addr,
input [7:0] mem_bus
);
parameter n = 24;
parameter j = 17; // Initialization is slow, runs at clk/2^(j+2) ~95Hz
parameter k = 11; // Writing/seeking is fast, clk/2^(k_2) ~6KHz
parameter noop = 6'b010000; // Allows LCD to drive lcd_d, can be safely written any time
reg [n:0] count = 0;
reg [5:0] lcd_state = noop;
reg init = 1; // Start in initialization on power on
reg row = 0; // Writing to top or or bottom row
assign mem_addr = {row, count[k+6:k+3]};
initial count[j+7:j+2] = 11;
always @ (posedge clk) begin
count <= count + 1;
if (init) begin // initalization
case (count[j+7:j+2])
1: lcd_state <= 6'b000010; // function set
2: lcd_state <= 6'b000010;
3: lcd_state <= 6'b001000;
4: lcd_state <= 6'b000000; // display on/off control
5: lcd_state <= 6'b001100;
6: lcd_state <= 6'b000000; // display clear
7: lcd_state <= 6'b000001;
8: lcd_state <= 6'b000000; // entry mode set
9: lcd_state <= 6'b000110;
10: begin init <= ~init; count <= 0; end
endcase
// Write lcd_state to the LCD and turn lcd_e high for the middle half of each lcd_state
{lcd_e,lcd_rs,lcd_rw,lcd_d[7:4]} <= {^count[j+1:j+0] & ~lcd_rw,lcd_state};
end else begin // Continuously update screen from memory
case (count[k+7:k+2])
32: lcd_state <= {3'b001,~row,2'b00}; // Move cursor to begining of next line
33: lcd_state <= 6'b000000;
34: begin count <= 0; row <= ~row; end // Restart and switch which row is being written
default: lcd_state <= {2'b10, ~count[k+2] ? mem_bus[7:4] : mem_bus[3:0]}; // Pull characters from bus
endcase
// Write lcd_state to the LCD and turn lcd_e high for the middle half of each lcd_state
{lcd_e,lcd_rs,lcd_rw,lcd_d[7:4]} <= {^count[k+1:k+0] & ~lcd_rw,lcd_state};
end
end
endmodule

37
spartanTest/logicUnitTB.v
View File

@ -1,37 +0,0 @@
module logicUnitTB ();
reg [2:0] opCode;
reg [3:0] A, B;
wire [3:0] resultA, resultO, resultX;
logicUnit uut (
.opCode(opCode),
.A(A),
.B(B),
.resultA(resultA),
.resultO(resultO),
.resultX(resultX)
);
initial begin
$dumpfile("logicUnit.vcd");
$dumpvars;
opCode = 3'b001; A = 4'b0001; B = 4'b0001; #2;
opCode = 3'b001; A = 4'b0011; B = 4'b0001; #2;
opCode = 3'b001; A = 4'b1001; B = 4'b1001; #2;
opCode = 3'b001; A = 4'b1111; B = 4'b1111; #2;
opCode = 3'b001; A = 4'b0000; B = 4'b0000; #2;
opCode = 3'b010; A = 4'b0001; B = 4'b0101; #2;
opCode = 3'b010; A = 4'b1001; B = 4'b0101; #2;
opCode = 3'b010; A = 4'b0001; B = 4'b1111; #2;
opCode = 3'b010; A = 4'b0000; B = 4'b0101; #2;
opCode = 3'b100; A = 4'b0000; B = 4'b0101; #2;
opCode = 3'b100; A = 4'b0000; B = 4'b0000; #2;
opCode = 3'b100; A = 4'b0000; B = 4'b0101; #2;
opCode = 3'b100; A = 4'b1111; B = 4'b1111; #2;
$finish;
end
endmodule

22
spartanTest/multiplierTB.v
View File

@ -1,22 +0,0 @@
module multiplierTB();
reg [3:0] A, B;
wire [7:0] Y;
multiplier uut(
.A(A),
.B(B),
.Y(Y)
);
initial begin
$dumpfile("multiplier.vcd");
$dumpvars;
A = 4'b0000; B = 4'b0000; #2;
A = 4'b0000; B = 4'b1000; #2;
A = 4'b1000; B = 4'b1000; #2;
A = 4'b0111; B = 4'b0111; #2;
A = 4'b1111; B = 4'b1111; #2;
$finish;
end
endmodule

26
spartanTest/opCodeTB.v
View File

@ -1,26 +0,0 @@
module opCodeTB();
reg [2:0] A;
wire [7:0] opCode;
opCode uut (
.A(A),
.opCode(opCode)
);
initial begin
$dumpfile("opCode.vcd");
$dumpvars;
A = 3'b000; #3;
A = 3'b001; #3;
A = 3'b010; #3;
A = 3'b011; #3;
A = 3'b100; #3;
A = 3'b101; #3;
A = 3'b110; #3;
A = 3'b111; #3;
$finish;
end
endmodule

140
spartanTest/selector
View File

@ -1,140 +0,0 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x558eb92edb80 .scope module, "selectorTB" "selectorTB" 2 1;
.timescale 0 0;
v0x558eb9317af0_0 .var "A", 3 0;
v0x558eb9317bd0_0 .var "ALUY", 7 0;
v0x558eb9317ca0_0 .var "B", 3 0;
v0x558eb9317da0_0 .net "Y", 7 0, v0x558eb9317740_0; 1 drivers
v0x558eb9317e70_0 .var "opCodeA", 2 0;
v0x558eb9317f60_0 .var "select", 1 0;
S_0x558eb9302140 .scope module, "uut" "selector" 2 9, 3 1 0, S_0x558eb92edb80;
.timescale 0 0;
.port_info 0 /INPUT 4 "A";
.port_info 1 /INPUT 4 "B";
.port_info 2 /INPUT 3 "opCodeA";
.port_info 3 /INPUT 2 "select";
.port_info 4 /INPUT 8 "ALUY";
.port_info 5 /OUTPUT 8 "Y";
v0x558eb9302350_0 .net "A", 3 0, v0x558eb9317af0_0; 1 drivers
v0x558eb93175a0_0 .net "ALUY", 7 0, v0x558eb9317bd0_0; 1 drivers
v0x558eb9317680_0 .net "B", 3 0, v0x558eb9317ca0_0; 1 drivers
v0x558eb9317740_0 .var "Y", 7 0;
v0x558eb9317820_0 .net "opCodeA", 2 0, v0x558eb9317e70_0; 1 drivers
v0x558eb9317950_0 .net "select", 1 0, v0x558eb9317f60_0; 1 drivers
E_0x558eb93001f0/0 .event edge, v0x558eb9317950_0, v0x558eb9302350_0, v0x558eb9317680_0, v0x558eb9317820_0;
E_0x558eb93001f0/1 .event edge, v0x558eb93175a0_0;
E_0x558eb93001f0 .event/or E_0x558eb93001f0/0, E_0x558eb93001f0/1;
.scope S_0x558eb9302140;
T_0 ;
%wait E_0x558eb93001f0;
%load/vec4 v0x558eb9317950_0;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_0.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_0.1, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_0.2, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_0.3, 6;
%pushi/vec4 0, 0, 8;
%store/vec4 v0x558eb9317740_0, 0, 8;
%jmp T_0.5;
T_0.0 ;
%pushi/vec4 0, 0, 4;
%load/vec4 v0x558eb9302350_0;
%concat/vec4; draw_concat_vec4
%store/vec4 v0x558eb9317740_0, 0, 8;
%jmp T_0.5;
T_0.1 ;
%pushi/vec4 0, 0, 4;
%load/vec4 v0x558eb9317680_0;
%concat/vec4; draw_concat_vec4
%store/vec4 v0x558eb9317740_0, 0, 8;
%jmp T_0.5;
T_0.2 ;
%pushi/vec4 0, 0, 5;
%load/vec4 v0x558eb9317820_0;
%concat/vec4; draw_concat_vec4
%store/vec4 v0x558eb9317740_0, 0, 8;
%jmp T_0.5;
T_0.3 ;
%load/vec4 v0x558eb93175a0_0;
%store/vec4 v0x558eb9317740_0, 0, 8;
%jmp T_0.5;
T_0.5 ;
%pop/vec4 1;
%jmp T_0;
.thread T_0, $push;
.scope S_0x558eb92edb80;
T_1 ;
%vpi_call 2 19 "$dumpfile", "selector.vcd" {0 0 0};
%vpi_call 2 20 "$dumpvars" {0 0 0};
%pushi/vec4 1, 0, 4;
%store/vec4 v0x558eb9317af0_0, 0, 4;
%pushi/vec4 2, 0, 4;
%store/vec4 v0x558eb9317ca0_0, 0, 4;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x558eb9317e70_0, 0, 3;
%pushi/vec4 240, 0, 8;
%store/vec4 v0x558eb9317bd0_0, 0, 8;
%pushi/vec4 0, 0, 2;
%store/vec4 v0x558eb9317f60_0, 0, 2;
%delay 5, 0;
%pushi/vec4 1, 0, 4;
%store/vec4 v0x558eb9317af0_0, 0, 4;
%pushi/vec4 2, 0, 4;
%store/vec4 v0x558eb9317ca0_0, 0, 4;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x558eb9317e70_0, 0, 3;
%pushi/vec4 240, 0, 8;
%store/vec4 v0x558eb9317bd0_0, 0, 8;
%pushi/vec4 1, 0, 2;
%store/vec4 v0x558eb9317f60_0, 0, 2;
%delay 5, 0;
%pushi/vec4 1, 0, 4;
%store/vec4 v0x558eb9317af0_0, 0, 4;
%pushi/vec4 2, 0, 4;
%store/vec4 v0x558eb9317ca0_0, 0, 4;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x558eb9317e70_0, 0, 3;
%pushi/vec4 112, 0, 8;
%store/vec4 v0x558eb9317bd0_0, 0, 8;
%pushi/vec4 2, 0, 2;
%store/vec4 v0x558eb9317f60_0, 0, 2;
%delay 5, 0;
%pushi/vec4 1, 0, 4;
%store/vec4 v0x558eb9317af0_0, 0, 4;
%pushi/vec4 2, 0, 4;
%store/vec4 v0x558eb9317ca0_0, 0, 4;
%pushi/vec4 7, 0, 3;
%store/vec4 v0x558eb9317e70_0, 0, 3;
%pushi/vec4 112, 0, 8;
%store/vec4 v0x558eb9317bd0_0, 0, 8;
%pushi/vec4 3, 0, 2;
%store/vec4 v0x558eb9317f60_0, 0, 2;
%delay 5, 0;
%vpi_call 2 25 "$finish" {0 0 0};
%end;
.thread T_1;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"selectorTB.v";
"selector.v";

20
spartanTest/selector.v
View File

@ -1,20 +0,0 @@
module selector (
input [3:0] A,
input [3:0] B,
input [2:0] opCodeA,
input [1:0] select,
input [7:0] ALUY,
output reg [7:0] Y
);
always @(*) begin
case (select)
2'b00: Y = {4'b0000, A}; // Zero-extend A to 8 bits
2'b01: Y = {4'b0000, B}; // Zero-extend B to 8 bits
2'b10: Y = {5'b00000, opCodeA}; // Zero-extend opCodeA to 8 bits
2'b11: Y = ALUY; // Directly assign ALUY
default: Y = 8'b00000000; // Default case for safety
endcase
end
endmodule

59
spartanTest/selector.vcd
View File

@ -1,59 +0,0 @@
$date
Sat Jan 18 17:21:23 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module selectorTB $end
$var wire 8 ! Y [7:0] $end
$var reg 4 " A [3:0] $end
$var reg 8 # ALUY [7:0] $end
$var reg 4 $ B [3:0] $end
$var reg 3 % opCodeA [2:0] $end
$var reg 2 & select [1:0] $end
$scope module uut $end
$var wire 4 ' A [3:0] $end
$var wire 8 ( ALUY [7:0] $end
$var wire 4 ) B [3:0] $end
$var wire 3 * opCodeA [2:0] $end
$var wire 2 + select [1:0] $end
$var reg 8 , Y [7:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b1 ,
b0 +
b111 *
b10 )
b11110000 (
b1 '
b0 &
b111 %
b10 $
b11110000 #
b1 "
b1 !
$end
#5
b10 !
b10 ,
b1 &
b1 +
#10
b111 !
b111 ,
b10 &
b10 +
b1110000 #
b1110000 (
#15
b1110000 !
b1110000 ,
b11 &
b11 +
#20

28
spartanTest/selectorTB.v
View File

@ -1,28 +0,0 @@
module selectorTB();
reg [1:0] select;
reg [3:0] A, B;
reg [7:0] ALUY;
reg [2:0] opCodeA;
wire [7:0] Y;
selector uut (
.select(select),
.A(A),
.B(B),
.opCodeA(opCodeA),
.ALUY(ALUY),
.Y(Y)
);
initial begin
$dumpfile("selector.vcd");
$dumpvars;
A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; ALUY = 8'b1111_0000; select = 2'b00; #5;
A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; ALUY = 8'b1111_0000; select = 2'b01; #5;
A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; ALUY = 8'b0111_0000; select = 2'b10; #5;
A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; ALUY = 8'b0111_0000; select = 2'b11; #5;
$finish;
end
endmodule

22
spartanTest/spartan3e.ucf
View File

@ -1,22 +0,0 @@
# Clock signal
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
# Slide Switches
NET "switches<0>" LOC = "L13" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "switches<1>" LOC = "L14" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "switches<2>" LOC = "H18" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "switches<3>" LOC = "N17" | IOSTANDARD = LVCMOS33 | PULLUP ;
# Rotary Encoder
NET "rot_a" LOC = "K18" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "rot_b" LOC = "G18" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "rot_center" LOC = "V16" | IOSTANDARD = LVCMOS33 | PULLDOWN ;
# LCD Interface
NET "lcd_e" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "lcd_rs" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "lcd_rw" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "lcd_d<4>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "lcd_d<5>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "lcd_d<6>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "lcd_d<7>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

41
spartanTest/subtractionTB.v
View File

@ -1,41 +0,0 @@
module subtractionTB;
reg [3:0] A, B;
reg BorrowIN;
wire [3:0] Y;
wire BorrowOUT;
// Instantiate the subtraction module
subtraction uut (
.A(A),
.B(B),
.BorrowIN(BorrowIN),
.Y(Y),
.BorrowOUT(BorrowOUT)
);
initial begin
$dumpfile("subtraction.vcd");
$dumpvars;
// Initialize inputs
A = 4'b0000; // Set A to 0
B = 4'b0000; // Set B to 0
BorrowIN = 0; // No borrow input
// Apply test cases
#10 A = 4'b0110; B = 4'b0010; BorrowIN = 0; // A = 6, B = 2
#10 A = 4'b0010; B = 4'b0110; BorrowIN = 0; // A = 2, B = 6
#10 A = 4'b1100; B = 4'b0100; BorrowIN = 0; // A = -4, B = 4
#10 A = 4'b1000; B = 4'b1000; BorrowIN = 0; // A = -8, B = -8
#10 A = 4'b1111; B = 4'b0001; BorrowIN = 1; // A = -1, B = 1, with borrow input
// Wait for the results
#10 $finish;
end
//initial begin
// Monitor the values of Y and overflow
// $monitor("At time %t: A = %b, B = %b, Y = %b, BorrowOut = %b, overflow = %b", $time, A, B, Y, BorrowOut, overflow);
//end
endmodule

61
spartanTest/switchRotary.v
View File

@ -1,61 +0,0 @@
module switchRotary(
input clk, // Clock signal
input [3:0] switches, // Slide switches SW3 to SW0
input rot_a, rot_b, // Rotary encoder signals
input rot_center, // Rotary encoder push button
output reg [3:0] A = 0, // Value of A
output reg [3:0] B = 0, // Value of B
output reg [2:0] opCode = 0 // Value of opCode
);
// Internal signals for rotary encoder
reg [1:0] rot_state = 2'b00;
reg [1:0] rot_prev = 2'b00;
// Selected register for modification
reg [1:0] selected = 2'b00; // 0 = A, 1 = B, 2 = opCode
// Debouncing for rotary center button
reg [15:0] debounce_counter = 0;
reg debounce_pressed = 0;
// Update selected register on rotary center press
always @(posedge clk) begin
if (rot_center && !debounce_pressed) begin
debounce_pressed <= 1;
selected <= selected + 1;
end
if (!rot_center) begin
debounce_pressed <= 0;
end
end
// Handle rotary encoder signals
always @(posedge clk) begin
rot_prev <= rot_state;
rot_state <= {rot_a, rot_b};
// Detect clockwise or counterclockwise rotation
if (rot_prev == 2'b01 && rot_state == 2'b11) begin
case (selected)
2'b00: if (A < 15) A <= A + 1;
2'b01: if (B < 15) B <= B + 1;
2'b10: if (opCode < 7) opCode <= opCode + 1;
endcase
end else if (rot_prev == 2'b11 && rot_state == 2'b01) begin
case (selected)
2'b00: if (A > 0) A <= A - 1;
2'b01: if (B > 0) B <= B - 1;
2'b10: if (opCode > 0) opCode <= opCode - 1;
endcase
end
end
// Update A, B, or opCode based on switches
always @(posedge clk) begin
case (switches)
4'b0001: A <= switches[3:0];
4'b0010: B <= switches[3:0];
4'b1000: opCode <= switches[2:0];
endcase
end
endmodule

62
spartanTest/top.v
View File

@ -1,62 +0,0 @@
module top (
input clk, // Clock signal
input [3:0] switches, // Slide switches SW3 to SW0
input rot_a, rot_b, // Rotary encoder signals
input rot_center, // Rotary encoder push button
output lcd_rs, // LCD Register Select
output lcd_rw, // LCD Read/Write
output lcd_e, // LCD Enable
output [7:4] lcd_d // LCD Data
);
// Internal signals
wire [3:0] A;
wire [3:0] B;
wire [2:0] opCode;
wire [7:0] Y;
wire [4:0] mem_addr;
wire [7:0] mem_bus;
// ALU Instance
ALU alu_inst (
.A(A),
.B(B),
.CarryIN(1'b0), // No carry-in for this implementation
.opCodeA(opCode),
.Y(Y),
.CarryOUT(), // Unused output
.overflow() // Unused output
);
// Switch and Rotary Controller
switch_and_rotary switch_rotary_inst (
.clk(clk),
.switches(switches),
.rot_a(rot_a),
.rot_b(rot_b),
.rot_center(rot_center),
.A(A),
.B(B),
.opCode(opCode)
);
// Character Memory
char_mem char_mem_inst (
.addr(mem_addr),
.bus(mem_bus),
.A(A),
.B(B),
.opCode(opCode),
.Y(Y)
);
// LCD Controller
lcd lcd_inst (
.clk(clk),
.lcd_rs(lcd_rs),
.lcd_rw(lcd_rw),
.lcd_e(lcd_e),
.lcd_d(lcd_d),
.mem_addr(mem_addr),
.mem_bus(mem_bus)
);
endmodule

2181
tangTest/ALU Normal file
View File

File diff suppressed because it is too large Load Diff

0
spartanTest/ALU.v → tangTest/ALU.v
View File

1086
tangTest/ALU.vcd Normal file
View File

File diff suppressed because it is too large Load Diff

26
tangTest/ALUtb.v Normal file
View File

@ -0,0 +1,26 @@
module ALUtb();
reg [3:0] A,B;
reg CarryIN;
reg [2:0] opCodeA;
wire CarryOUT, overflow;
wire [7:0] Y;
ALU uut (
.A(A),
.B(B),
.CarryIN(CarryIN),
.opCodeA(opCodeA),
.CarryOUT(CarryOUT),
.overflow(overflow),
.Y(Y)
);
initial begin
$dumpfile("ALU.vcd");
$dumpvars;
A = 4'b1111; B = 4'b0001; CarryIN = 1'b0; opCodeA = 3'b001; #5;
$finish;
end
endmodule

0
spartanTest/BinaryToBCD.v → tangTest/BinaryToBCD.v
View File

0
spartanTest/addition.v → tangTest/addition.v
View File

0
spartanTest/arithmeticUnit.v → tangTest/arithmeticUnit.v
View File

2220
tangTest/bttn Normal file
View File

File diff suppressed because it is too large Load Diff

59
tangTest/bttn.cst Normal file
View File

@ -0,0 +1,59 @@
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Physical Constraints file
//Tool Version: V1.9.9.03 Education (64-bit)
//Part Number: GW2A-LV18PG256C8/I7
//Device: GW2A-18
//Device Version: C
//Created Time: Sat 01 18 21:56:09 2025
IO_LOC "Y[11]" B12;
IO_PORT "Y[11]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[10]" B13;
IO_PORT "Y[10]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[9]" B14;
IO_PORT "Y[9]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[8]" D14;
IO_PORT "Y[8]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[7]" J14;
IO_PORT "Y[7]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[6]" M14;
IO_PORT "Y[6]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[5]" T12;
IO_PORT "Y[5]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[4]" T11;
IO_PORT "Y[4]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[3]" P9;
IO_PORT "Y[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[2]" P8;
IO_PORT "Y[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[1]" T7;
IO_PORT "Y[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[0]" P6;
IO_PORT "Y[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "select[1]" A14;
IO_PORT "select[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "select[0]" A15;
IO_PORT "select[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[2]" E8;
IO_PORT "opCodeA[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[1]" T4;
IO_PORT "opCodeA[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[0]" T5;
IO_PORT "opCodeA[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "B[3]" N8;
IO_PORT "B[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[2]" N7;
IO_PORT "B[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[1]" D11;
IO_PORT "B[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[0]" B11;
IO_PORT "B[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[3]" L9;
IO_PORT "A[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[2]" E15;
IO_PORT "A[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[1]" N6;
IO_PORT "A[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[0]" A11;
IO_PORT "A[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;

20
tangTest/bttn.v Normal file
View File

@ -0,0 +1,20 @@
module bttn (
input [3:0] A, B,
input [2:0] opCodeA,
input [1:0] select,
output [1:0] led,
output [11:0] Y
);
wire wire1, wire2;
wire [11:0] selectY;
ALU a1( .A(A),
.B(B),
.opCodeA(opCodeA),
.CarryIN(1'b0),
.bcd(selectY),
.CarryOUT(led[0]),
.overflow(led[1]));
selector s1(.A(A), .B(B), .opCodeA(opCodeA), .select(select), .ALUY(selectY), .Y(Y));
endmodule

1493
tangTest/bttn.vcd Normal file
View File

File diff suppressed because it is too large Load Diff

28
tangTest/bttnTB.v Normal file
View File

@ -0,0 +1,28 @@
module bttnTB();
reg [3:0] A,B;
reg [2:0] opCodeA;
reg [1:0] select;
wire [1:0] led;
wire [11:0] Y;
bttn uut (
.A(A),
.B(B),
.opCodeA(opCodeA),
.select(select),
.led(led),
.Y(Y)
);
initial begin
$dumpfile("bttn.vcd");
$dumpvars;
A = 4'b1111; B = 4'b1111; opCodeA = 3'b000; select = 2'b01; #5;
A = 4'b0000; B = 4'b1111; opCodeA = 3'b001; select = 2'b01; #5;
A = 4'b1111; B = 4'b0001; opCodeA = 3'b001; select = 2'b01; #5;
A = 4'b1111; B = 4'b0001; opCodeA = 3'b001; select = 2'b11; #5;
$finish;
end
endmodule

0
spartanTest/dabble.v → tangTest/dabble.v
View File

0
spartanTest/fulladder.v → tangTest/fulladder.v
View File

0
spartanTest/fullsubtraction.v → tangTest/fullsubtraction.v
View File

0
spartanTest/halfadder.v → tangTest/halfadder.v
View File

0
spartanTest/halfsubtraction.v → tangTest/halfsubtraction.v
View File

0
spartanTest/logicUnit.v → tangTest/logicUnit.v
View File

782
tangTest/mult Normal file
View File

@ -0,0 +1,782 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x560808805dd0 .scope module, "multTB" "multTB" 2 1;
.timescale 0 0;
v0x56080883b1b0_0 .var "A", 3 0;
v0x56080883b2a0_0 .var "B", 3 0;
v0x56080883b370_0 .net "Y", 7 0, L_0x560808846dd0; 1 drivers
S_0x560808804330 .scope module, "uut" "multiplier" 2 6, 3 1 0, S_0x560808805dd0;
.timescale 0 0;
.port_info 0 /INPUT 4 "A";
.port_info 1 /INPUT 4 "B";
.port_info 2 /OUTPUT 8 "Y";
L_0x56080883b470 .functor AND 1, L_0x56080883b570, L_0x56080883b660, C4<1>, C4<1>;
L_0x56080883b7a0 .functor AND 1, L_0x56080883b810, L_0x56080883b900, C4<1>, C4<1>;
L_0x56080883ba20 .functor AND 1, L_0x56080883ba90, L_0x56080883bb80, C4<1>, C4<1>;
L_0x56080883bc60 .functor AND 1, L_0x56080883bd00, L_0x56080883bda0, C4<1>, C4<1>;
L_0x7f3ea6b4d018 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
L_0x56080883c0c0 .functor NOT 1, L_0x7f3ea6b4d018, C4<0>, C4<0>, C4<0>;
L_0x56080883c1d0 .functor AND 1, L_0x56080883c280, L_0x56080883c3d0, C4<1>, C4<1>;
L_0x56080883c470 .functor AND 1, L_0x56080883c4e0, L_0x56080883c640, C4<1>, C4<1>;
L_0x56080883c730 .functor AND 1, L_0x56080883c7f0, L_0x56080883c960, C4<1>, C4<1>;
L_0x56080883c5d0 .functor AND 1, L_0x56080883cd10, L_0x56080883ce00, C4<1>, C4<1>;
L_0x56080883ef10 .functor AND 1, L_0x56080883f360, L_0x56080883cef0, C4<1>, C4<1>;
L_0x56080883f4b0 .functor AND 1, L_0x56080883f520, L_0x56080883f680, C4<1>, C4<1>;
L_0x56080883f720 .functor AND 1, L_0x56080883f800, L_0x56080883f9c0, C4<1>, C4<1>;
L_0x56080883fd70 .functor AND 1, L_0x56080883fe30, L_0x56080883ff20, C4<1>, C4<1>;
L_0x5608088423d0 .functor AND 1, L_0x5608088429c0, L_0x560808842a60, C4<1>, C4<1>;
L_0x56080883f790 .functor AND 1, L_0x560808842c10, L_0x560808842cb0, C4<1>, C4<1>;
L_0x560808842ec0 .functor AND 1, L_0x560808842fc0, L_0x5608088430b0, C4<1>, C4<1>;
L_0x5608088435d0 .functor AND 1, L_0x560808843690, L_0x5608088438c0, C4<1>, C4<1>;
L_0x7f3ea6b4d138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x560808845900 .functor OR 1, L_0x560808845f60, L_0x7f3ea6b4d138, C4<0>, C4<0>;
L_0x7f3ea6b4d180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x560808846160 .functor OR 1, L_0x5608088461d0, L_0x7f3ea6b4d180, C4<0>, C4<0>;
L_0x7f3ea6b4d1c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x560808846310 .functor OR 1, L_0x560808845ec0, L_0x7f3ea6b4d1c8, C4<0>, C4<0>;
L_0x7f3ea6b4d210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x560808846690 .functor OR 1, L_0x560808846700, L_0x7f3ea6b4d210, C4<0>, C4<0>;
L_0x7f3ea6b4d258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x560808846840 .functor OR 1, L_0x560808846970, L_0x7f3ea6b4d258, C4<0>, C4<0>;
L_0x7f3ea6b4d2a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x560808846c70 .functor OR 1, L_0x560808846ce0, L_0x7f3ea6b4d2a0, C4<0>, C4<0>;
L_0x7f3ea6b4d2e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
L_0x5608088472d0 .functor OR 1, L_0x560808847460, L_0x7f3ea6b4d2e8, C4<0>, C4<0>;
v0x560808836240_0 .net "A", 3 0, v0x56080883b1b0_0; 1 drivers
v0x560808836340_0 .net "B", 3 0, v0x56080883b2a0_0; 1 drivers
v0x560808836420_0 .net "S0", 4 0, L_0x56080883f1d0; 1 drivers
v0x5608088364e0_0 .net "S1", 4 0, L_0x560808842710; 1 drivers
v0x5608088365c0_0 .net "S2", 4 0, L_0x560808845d90; 1 drivers
v0x5608088366f0_0 .net "Y", 7 0, L_0x560808846dd0; alias, 1 drivers
v0x5608088367d0_0 .net *"_ivl_1", 0 0, L_0x56080883b470; 1 drivers
v0x5608088368b0_0 .net *"_ivl_10", 0 0, L_0x56080883b810; 1 drivers
v0x560808836990_0 .net *"_ivl_101", 0 0, L_0x560808842a60; 1 drivers
v0x560808836a70_0 .net *"_ivl_102", 0 0, L_0x56080883f790; 1 drivers
v0x560808836b50_0 .net *"_ivl_105", 0 0, L_0x560808842c10; 1 drivers
v0x560808836c30_0 .net *"_ivl_107", 0 0, L_0x560808842cb0; 1 drivers
v0x560808836d10_0 .net *"_ivl_108", 0 0, L_0x560808842ec0; 1 drivers
v0x560808836df0_0 .net *"_ivl_111", 0 0, L_0x560808842fc0; 1 drivers
v0x560808836ed0_0 .net *"_ivl_113", 0 0, L_0x5608088430b0; 1 drivers
v0x560808836fb0_0 .net *"_ivl_114", 0 0, L_0x5608088435d0; 1 drivers
v0x560808837090_0 .net *"_ivl_118", 0 0, L_0x560808843690; 1 drivers
v0x560808837170_0 .net *"_ivl_12", 0 0, L_0x56080883b900; 1 drivers
v0x560808837250_0 .net *"_ivl_120", 0 0, L_0x5608088438c0; 1 drivers
v0x560808837330_0 .net *"_ivl_13", 0 0, L_0x56080883ba20; 1 drivers
v0x560808837410_0 .net *"_ivl_130", 0 0, L_0x560808845900; 1 drivers
v0x5608088374f0_0 .net *"_ivl_133", 0 0, L_0x560808845f60; 1 drivers
v0x5608088375d0_0 .net/2u *"_ivl_134", 0 0, L_0x7f3ea6b4d138; 1 drivers
v0x5608088376b0_0 .net *"_ivl_136", 0 0, L_0x560808846160; 1 drivers
v0x560808837790_0 .net *"_ivl_139", 0 0, L_0x5608088461d0; 1 drivers
v0x560808837870_0 .net/2u *"_ivl_140", 0 0, L_0x7f3ea6b4d180; 1 drivers
v0x560808837950_0 .net *"_ivl_142", 0 0, L_0x560808846310; 1 drivers
v0x560808837a30_0 .net *"_ivl_145", 0 0, L_0x560808845ec0; 1 drivers
v0x560808837b10_0 .net/2u *"_ivl_146", 0 0, L_0x7f3ea6b4d1c8; 1 drivers
v0x560808837bf0_0 .net *"_ivl_148", 0 0, L_0x560808846690; 1 drivers
v0x560808837cd0_0 .net *"_ivl_151", 0 0, L_0x560808846700; 1 drivers
v0x560808837db0_0 .net/2u *"_ivl_152", 0 0, L_0x7f3ea6b4d210; 1 drivers
v0x560808837e90_0 .net *"_ivl_154", 0 0, L_0x560808846840; 1 drivers
v0x560808838180_0 .net *"_ivl_157", 0 0, L_0x560808846970; 1 drivers
v0x560808838260_0 .net/2u *"_ivl_158", 0 0, L_0x7f3ea6b4d258; 1 drivers
v0x560808838340_0 .net *"_ivl_16", 0 0, L_0x56080883ba90; 1 drivers
v0x560808838420_0 .net *"_ivl_160", 0 0, L_0x560808846c70; 1 drivers
v0x560808838500_0 .net *"_ivl_163", 0 0, L_0x560808846ce0; 1 drivers
v0x5608088385e0_0 .net/2u *"_ivl_164", 0 0, L_0x7f3ea6b4d2a0; 1 drivers
v0x5608088386c0_0 .net *"_ivl_166", 0 0, L_0x5608088472d0; 1 drivers
v0x5608088387a0_0 .net *"_ivl_170", 0 0, L_0x560808847460; 1 drivers
v0x560808838880_0 .net/2u *"_ivl_171", 0 0, L_0x7f3ea6b4d2e8; 1 drivers
v0x560808838960_0 .net *"_ivl_18", 0 0, L_0x56080883bb80; 1 drivers
v0x560808838a40_0 .net *"_ivl_19", 0 0, L_0x56080883bc60; 1 drivers
v0x560808838b20_0 .net *"_ivl_22", 0 0, L_0x56080883bd00; 1 drivers
v0x560808838c00_0 .net *"_ivl_24", 0 0, L_0x56080883bda0; 1 drivers
v0x560808838ce0_0 .net *"_ivl_25", 0 0, L_0x56080883c0c0; 1 drivers
v0x560808838dc0_0 .net/2u *"_ivl_28", 0 0, L_0x7f3ea6b4d018; 1 drivers
v0x560808838ea0_0 .net *"_ivl_30", 0 0, L_0x56080883c1d0; 1 drivers
v0x560808838f80_0 .net *"_ivl_33", 0 0, L_0x56080883c280; 1 drivers
v0x560808839060_0 .net *"_ivl_35", 0 0, L_0x56080883c3d0; 1 drivers
v0x560808839140_0 .net *"_ivl_36", 0 0, L_0x56080883c470; 1 drivers
v0x560808839220_0 .net *"_ivl_39", 0 0, L_0x56080883c4e0; 1 drivers
v0x560808839300_0 .net *"_ivl_4", 0 0, L_0x56080883b570; 1 drivers
v0x5608088393e0_0 .net *"_ivl_41", 0 0, L_0x56080883c640; 1 drivers
v0x5608088394c0_0 .net *"_ivl_42", 0 0, L_0x56080883c730; 1 drivers
v0x5608088395a0_0 .net *"_ivl_45", 0 0, L_0x56080883c7f0; 1 drivers
v0x560808839680_0 .net *"_ivl_47", 0 0, L_0x56080883c960; 1 drivers
v0x560808839760_0 .net *"_ivl_48", 0 0, L_0x56080883c5d0; 1 drivers
v0x560808839840_0 .net *"_ivl_52", 0 0, L_0x56080883cd10; 1 drivers
v0x560808839920_0 .net *"_ivl_54", 0 0, L_0x56080883ce00; 1 drivers
v0x560808839a00_0 .net *"_ivl_6", 0 0, L_0x56080883b660; 1 drivers
v0x560808839ae0_0 .net *"_ivl_62", 0 0, L_0x56080883ef10; 1 drivers
v0x560808839bc0_0 .net *"_ivl_65", 0 0, L_0x56080883f360; 1 drivers
v0x560808839ca0_0 .net *"_ivl_67", 0 0, L_0x56080883cef0; 1 drivers
v0x56080883a190_0 .net *"_ivl_68", 0 0, L_0x56080883f4b0; 1 drivers
v0x56080883a270_0 .net *"_ivl_7", 0 0, L_0x56080883b7a0; 1 drivers
v0x56080883a350_0 .net *"_ivl_71", 0 0, L_0x56080883f520; 1 drivers
v0x56080883a430_0 .net *"_ivl_73", 0 0, L_0x56080883f680; 1 drivers
v0x56080883a510_0 .net *"_ivl_74", 0 0, L_0x56080883f720; 1 drivers
v0x56080883a5f0_0 .net *"_ivl_77", 0 0, L_0x56080883f800; 1 drivers
v0x56080883a6d0_0 .net *"_ivl_79", 0 0, L_0x56080883f9c0; 1 drivers
v0x56080883a7b0_0 .net *"_ivl_80", 0 0, L_0x56080883fd70; 1 drivers
v0x56080883a890_0 .net *"_ivl_84", 0 0, L_0x56080883fe30; 1 drivers
v0x56080883a970_0 .net *"_ivl_86", 0 0, L_0x56080883ff20; 1 drivers
v0x56080883aa50_0 .net *"_ivl_96", 0 0, L_0x5608088423d0; 1 drivers
v0x56080883ab30_0 .net *"_ivl_99", 0 0, L_0x5608088429c0; 1 drivers
v0x56080883ac10_0 .net "a0", 3 0, L_0x56080883ca50; 1 drivers
v0x56080883acd0_0 .net "a1", 3 0, L_0x56080883fab0; 1 drivers
v0x56080883ada0_0 .net "a2", 3 0, L_0x560808842da0; 1 drivers
v0x56080883ae70_0 .net "b0", 3 0, L_0x56080883bee0; 1 drivers
v0x56080883af40_0 .net "overflow0", 0 0, L_0x56080883f020; 1 drivers
v0x56080883b010_0 .net "overflow1", 0 0, L_0x5608088424e0; 1 drivers
v0x56080883b0e0_0 .net "overflow2", 0 0, L_0x560808845a10; 1 drivers
L_0x56080883b570 .part v0x56080883b1b0_0, 0, 1;
L_0x56080883b660 .part v0x56080883b2a0_0, 0, 1;
L_0x56080883b810 .part v0x56080883b1b0_0, 1, 1;
L_0x56080883b900 .part v0x56080883b2a0_0, 0, 1;
L_0x56080883ba90 .part v0x56080883b1b0_0, 2, 1;
L_0x56080883bb80 .part v0x56080883b2a0_0, 0, 1;
L_0x56080883bd00 .part v0x56080883b1b0_0, 3, 1;
L_0x56080883bda0 .part v0x56080883b2a0_0, 0, 1;
L_0x56080883bee0 .concat8 [ 1 1 1 1], L_0x56080883b7a0, L_0x56080883ba20, L_0x56080883bc60, L_0x56080883c0c0;
L_0x56080883c280 .part v0x56080883b1b0_0, 0, 1;
L_0x56080883c3d0 .part v0x56080883b2a0_0, 1, 1;
L_0x56080883c4e0 .part v0x56080883b1b0_0, 1, 1;
L_0x56080883c640 .part v0x56080883b2a0_0, 1, 1;
L_0x56080883c7f0 .part v0x56080883b1b0_0, 2, 1;
L_0x56080883c960 .part v0x56080883b2a0_0, 1, 1;
L_0x56080883ca50 .concat8 [ 1 1 1 1], L_0x56080883c1d0, L_0x56080883c470, L_0x56080883c730, L_0x56080883c5d0;
L_0x56080883cd10 .part v0x56080883b1b0_0, 3, 1;
L_0x56080883ce00 .part v0x56080883b2a0_0, 1, 1;
L_0x56080883f1d0 .concat8 [ 4 1 0 0], L_0x56080883ef80, L_0x56080883e990;
L_0x56080883f360 .part v0x56080883b1b0_0, 0, 1;
L_0x56080883cef0 .part v0x56080883b2a0_0, 2, 1;
L_0x56080883f520 .part v0x56080883b1b0_0, 1, 1;
L_0x56080883f680 .part v0x56080883b2a0_0, 2, 1;
L_0x56080883f800 .part v0x56080883b1b0_0, 2, 1;
L_0x56080883f9c0 .part v0x56080883b2a0_0, 2, 1;
L_0x56080883fab0 .concat8 [ 1 1 1 1], L_0x56080883ef10, L_0x56080883f4b0, L_0x56080883f720, L_0x56080883fd70;
L_0x56080883fe30 .part v0x56080883b1b0_0, 3, 1;
L_0x56080883ff20 .part v0x56080883b2a0_0, 2, 1;
L_0x560808842670 .part L_0x56080883f1d0, 1, 4;
L_0x560808842710 .concat8 [ 4 1 0 0], L_0x560808842440, L_0x560808841dc0;
L_0x5608088429c0 .part v0x56080883b1b0_0, 0, 1;
L_0x560808842a60 .part v0x56080883b2a0_0, 3, 1;
L_0x560808842c10 .part v0x56080883b1b0_0, 1, 1;
L_0x560808842cb0 .part v0x56080883b2a0_0, 3, 1;
L_0x560808842fc0 .part v0x56080883b1b0_0, 2, 1;
L_0x5608088430b0 .part v0x56080883b2a0_0, 3, 1;
L_0x560808842da0 .concat8 [ 1 1 1 1], L_0x5608088423d0, L_0x56080883f790, L_0x560808842ec0, L_0x5608088435d0;
L_0x560808843690 .part v0x56080883b1b0_0, 3, 1;
L_0x5608088438c0 .part v0x56080883b2a0_0, 3, 1;
L_0x560808845ba0 .part L_0x560808842710, 1, 4;
L_0x560808845d90 .concat8 [ 4 1 0 0], L_0x560808845970, L_0x560808845330;
L_0x560808845f60 .part L_0x56080883f1d0, 0, 1;
L_0x5608088461d0 .part L_0x560808842710, 0, 1;
L_0x560808845ec0 .part L_0x560808845d90, 0, 1;
L_0x560808846700 .part L_0x560808845d90, 1, 1;
L_0x560808846970 .part L_0x560808845d90, 2, 1;
L_0x560808846ce0 .part L_0x560808845d90, 3, 1;
LS_0x560808846dd0_0_0 .concat8 [ 1 1 1 1], L_0x56080883b470, L_0x560808845900, L_0x560808846160, L_0x560808846310;
LS_0x560808846dd0_0_4 .concat8 [ 1 1 1 1], L_0x560808846690, L_0x560808846840, L_0x560808846c70, L_0x5608088472d0;
L_0x560808846dd0 .concat8 [ 4 4 0 0], LS_0x560808846dd0_0_0, LS_0x560808846dd0_0_4;
L_0x560808847460 .part L_0x560808845d90, 4, 1;
S_0x5608087fbca0 .scope module, "add0" "addition" 3 26, 4 1 0, S_0x560808804330;
.timescale 0 0;
.port_info 0 /INPUT 4 "A";
.port_info 1 /INPUT 4 "B";
.port_info 2 /INPUT 1 "CarryIN";
.port_info 3 /OUTPUT 4 "Y";
.port_info 4 /OUTPUT 1 "CarryOUT";
.port_info 5 /OUTPUT 1 "overflow";
L_0x56080883f020 .functor XOR 1, L_0x56080883f090, L_0x56080883e990, C4<0>, C4<0>;
v0x560808829b90_0 .net "A", 3 0, L_0x56080883ca50; alias, 1 drivers
v0x560808829c70_0 .net "B", 3 0, L_0x56080883bee0; alias, 1 drivers
v0x560808829d50_0 .net "Carry4", 2 0, L_0x56080883e400; 1 drivers
L_0x7f3ea6b4d060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x560808829e10_0 .net "CarryIN", 0 0, L_0x7f3ea6b4d060; 1 drivers
v0x560808829f00_0 .net "CarryOUT", 0 0, L_0x56080883e990; 1 drivers
v0x560808829ff0_0 .net "Y", 3 0, L_0x56080883ef80; 1 drivers
v0x56080882a0b0_0 .net *"_ivl_39", 0 0, L_0x56080883f090; 1 drivers
v0x56080882a190_0 .net "overflow", 0 0, L_0x56080883f020; alias, 1 drivers
L_0x56080883d300 .part L_0x56080883ca50, 0, 1;
L_0x56080883d3a0 .part L_0x56080883bee0, 0, 1;
L_0x56080883d830 .part L_0x56080883ca50, 1, 1;
L_0x56080883d9f0 .part L_0x56080883bee0, 1, 1;
L_0x56080883dbb0 .part L_0x56080883e400, 0, 1;
L_0x56080883dfe0 .part L_0x56080883ca50, 2, 1;
L_0x56080883e150 .part L_0x56080883bee0, 2, 1;
L_0x56080883e280 .part L_0x56080883e400, 1, 1;
L_0x56080883e400 .concat8 [ 1 1 1 0], L_0x56080883d290, L_0x56080883d7c0, L_0x56080883df50;
L_0x56080883ea90 .part L_0x56080883ca50, 3, 1;
L_0x56080883ec20 .part L_0x56080883bee0, 3, 1;
L_0x56080883ed50 .part L_0x56080883e400, 2, 1;
L_0x56080883ef80 .concat8 [ 1 1 1 1], L_0x56080883d220, L_0x56080883d700, L_0x56080883dec0, L_0x56080883e8b0;
L_0x56080883f090 .part L_0x56080883e400, 2, 1;
S_0x5608087fa200 .scope module, "f0" "fulladder" 4 11, 5 1 0, S_0x5608087fbca0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x56080883d290 .functor OR 1, L_0x56080883cf90, L_0x56080883d160, C4<0>, C4<0>;
v0x560808825840_0 .net "A", 0 0, L_0x56080883d300; 1 drivers
v0x560808825900_0 .net "B", 0 0, L_0x56080883d3a0; 1 drivers
v0x5608088259d0_0 .net "Carry", 0 0, L_0x7f3ea6b4d060; alias, 1 drivers
v0x560808825ad0_0 .net "CarryO", 0 0, L_0x56080883d290; 1 drivers
v0x560808825b70_0 .net "Sum", 0 0, L_0x56080883d220; 1 drivers
v0x560808825c60_0 .net "and1", 0 0, L_0x56080883cf90; 1 drivers
v0x560808825d30_0 .net "and2", 0 0, L_0x56080883d160; 1 drivers
v0x560808825e00_0 .net "xor1", 0 0, L_0x56080883d0f0; 1 drivers
S_0x5608087f1eb0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x5608087fa200;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x56080883cf90 .functor AND 1, L_0x56080883d300, L_0x56080883d3a0, C4<1>, C4<1>;
L_0x56080883d0f0 .functor XOR 1, L_0x56080883d300, L_0x56080883d3a0, C4<0>, C4<0>;
v0x56080880a2e0_0 .net "A", 0 0, L_0x56080883d300; alias, 1 drivers
v0x560808809740_0 .net "B", 0 0, L_0x56080883d3a0; alias, 1 drivers
v0x560808808a00_0 .net "Carry", 0 0, L_0x56080883cf90; alias, 1 drivers
v0x56080878a680_0 .net "Sum", 0 0, L_0x56080883d0f0; alias, 1 drivers
S_0x5608088252c0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x5608087fa200;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x56080883d160 .functor AND 1, L_0x56080883d0f0, L_0x7f3ea6b4d060, C4<1>, C4<1>;
L_0x56080883d220 .functor XOR 1, L_0x56080883d0f0, L_0x7f3ea6b4d060, C4<0>, C4<0>;
v0x5608088254c0_0 .net "A", 0 0, L_0x56080883d0f0; alias, 1 drivers
v0x560808825560_0 .net "B", 0 0, L_0x7f3ea6b4d060; alias, 1 drivers
v0x560808825600_0 .net "Carry", 0 0, L_0x56080883d160; alias, 1 drivers
v0x5608088256d0_0 .net "Sum", 0 0, L_0x56080883d220; alias, 1 drivers
S_0x560808825ef0 .scope module, "f1" "fulladder" 4 12, 5 1 0, S_0x5608087fbca0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x56080883d7c0 .functor OR 1, L_0x56080883d4d0, L_0x56080883d5b0, C4<0>, C4<0>;
v0x560808826c70_0 .net "A", 0 0, L_0x56080883d830; 1 drivers
v0x560808826d30_0 .net "B", 0 0, L_0x56080883d9f0; 1 drivers
v0x560808826e00_0 .net "Carry", 0 0, L_0x56080883dbb0; 1 drivers
v0x560808826f00_0 .net "CarryO", 0 0, L_0x56080883d7c0; 1 drivers
v0x560808826fa0_0 .net "Sum", 0 0, L_0x56080883d700; 1 drivers
v0x560808827090_0 .net "and1", 0 0, L_0x56080883d4d0; 1 drivers
v0x560808827160_0 .net "and2", 0 0, L_0x56080883d5b0; 1 drivers
v0x560808827230_0 .net "xor1", 0 0, L_0x56080883d540; 1 drivers
S_0x5608088260d0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808825ef0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x56080883d4d0 .functor AND 1, L_0x56080883d830, L_0x56080883d9f0, C4<1>, C4<1>;
L_0x56080883d540 .functor XOR 1, L_0x56080883d830, L_0x56080883d9f0, C4<0>, C4<0>;
v0x5608088262e0_0 .net "A", 0 0, L_0x56080883d830; alias, 1 drivers
v0x5608088263c0_0 .net "B", 0 0, L_0x56080883d9f0; alias, 1 drivers
v0x560808826480_0 .net "Carry", 0 0, L_0x56080883d4d0; alias, 1 drivers
v0x560808826550_0 .net "Sum", 0 0, L_0x56080883d540; alias, 1 drivers
S_0x5608088266c0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808825ef0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x56080883d5b0 .functor AND 1, L_0x56080883d540, L_0x56080883dbb0, C4<1>, C4<1>;
L_0x56080883d700 .functor XOR 1, L_0x56080883d540, L_0x56080883dbb0, C4<0>, C4<0>;
v0x5608088268c0_0 .net "A", 0 0, L_0x56080883d540; alias, 1 drivers
v0x560808826990_0 .net "B", 0 0, L_0x56080883dbb0; alias, 1 drivers
v0x560808826a30_0 .net "Carry", 0 0, L_0x56080883d5b0; alias, 1 drivers
v0x560808826b00_0 .net "Sum", 0 0, L_0x56080883d700; alias, 1 drivers
S_0x560808827320 .scope module, "f2" "fulladder" 4 13, 5 1 0, S_0x5608087fbca0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x56080883df50 .functor OR 1, L_0x56080883dce0, L_0x56080883ddc0, C4<0>, C4<0>;
v0x5608088280b0_0 .net "A", 0 0, L_0x56080883dfe0; 1 drivers
v0x560808828170_0 .net "B", 0 0, L_0x56080883e150; 1 drivers
v0x560808828240_0 .net "Carry", 0 0, L_0x56080883e280; 1 drivers
v0x560808828340_0 .net "CarryO", 0 0, L_0x56080883df50; 1 drivers
v0x5608088283e0_0 .net "Sum", 0 0, L_0x56080883dec0; 1 drivers
v0x5608088284d0_0 .net "and1", 0 0, L_0x56080883dce0; 1 drivers
v0x5608088285a0_0 .net "and2", 0 0, L_0x56080883ddc0; 1 drivers
v0x560808828670_0 .net "xor1", 0 0, L_0x56080883dd50; 1 drivers
S_0x560808827530 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808827320;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x56080883dce0 .functor AND 1, L_0x56080883dfe0, L_0x56080883e150, C4<1>, C4<1>;
L_0x56080883dd50 .functor XOR 1, L_0x56080883dfe0, L_0x56080883e150, C4<0>, C4<0>;
v0x560808827740_0 .net "A", 0 0, L_0x56080883dfe0; alias, 1 drivers
v0x560808827800_0 .net "B", 0 0, L_0x56080883e150; alias, 1 drivers
v0x5608088278c0_0 .net "Carry", 0 0, L_0x56080883dce0; alias, 1 drivers
v0x560808827990_0 .net "Sum", 0 0, L_0x56080883dd50; alias, 1 drivers
S_0x560808827b00 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808827320;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x56080883ddc0 .functor AND 1, L_0x56080883dd50, L_0x56080883e280, C4<1>, C4<1>;
L_0x56080883dec0 .functor XOR 1, L_0x56080883dd50, L_0x56080883e280, C4<0>, C4<0>;
v0x560808827d00_0 .net "A", 0 0, L_0x56080883dd50; alias, 1 drivers
v0x560808827dd0_0 .net "B", 0 0, L_0x56080883e280; alias, 1 drivers
v0x560808827e70_0 .net "Carry", 0 0, L_0x56080883ddc0; alias, 1 drivers
v0x560808827f40_0 .net "Sum", 0 0, L_0x56080883dec0; alias, 1 drivers
S_0x560808828760 .scope module, "f3" "fulladder" 4 14, 5 1 0, S_0x5608087fbca0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x56080883e990 .functor OR 1, L_0x56080883e4f0, L_0x56080883e720, C4<0>, C4<0>;
v0x5608088294e0_0 .net "A", 0 0, L_0x56080883ea90; 1 drivers
v0x5608088295a0_0 .net "B", 0 0, L_0x56080883ec20; 1 drivers
v0x560808829670_0 .net "Carry", 0 0, L_0x56080883ed50; 1 drivers
v0x560808829770_0 .net "CarryO", 0 0, L_0x56080883e990; alias, 1 drivers
v0x560808829810_0 .net "Sum", 0 0, L_0x56080883e8b0; 1 drivers
v0x560808829900_0 .net "and1", 0 0, L_0x56080883e4f0; 1 drivers
v0x5608088299d0_0 .net "and2", 0 0, L_0x56080883e720; 1 drivers
v0x560808829aa0_0 .net "xor1", 0 0, L_0x56080883e690; 1 drivers
S_0x560808828940 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808828760;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x56080883e4f0 .functor AND 1, L_0x56080883ea90, L_0x56080883ec20, C4<1>, C4<1>;
L_0x56080883e690 .functor XOR 1, L_0x56080883ea90, L_0x56080883ec20, C4<0>, C4<0>;
v0x560808828b50_0 .net "A", 0 0, L_0x56080883ea90; alias, 1 drivers
v0x560808828c30_0 .net "B", 0 0, L_0x56080883ec20; alias, 1 drivers
v0x560808828cf0_0 .net "Carry", 0 0, L_0x56080883e4f0; alias, 1 drivers
v0x560808828dc0_0 .net "Sum", 0 0, L_0x56080883e690; alias, 1 drivers
S_0x560808828f30 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808828760;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x56080883e720 .functor AND 1, L_0x56080883e690, L_0x56080883ed50, C4<1>, C4<1>;
L_0x56080883e8b0 .functor XOR 1, L_0x56080883e690, L_0x56080883ed50, C4<0>, C4<0>;
v0x560808829130_0 .net "A", 0 0, L_0x56080883e690; alias, 1 drivers
v0x560808829200_0 .net "B", 0 0, L_0x56080883ed50; alias, 1 drivers
v0x5608088292a0_0 .net "Carry", 0 0, L_0x56080883e720; alias, 1 drivers
v0x560808829370_0 .net "Sum", 0 0, L_0x56080883e8b0; alias, 1 drivers
S_0x56080882a310 .scope module, "add1" "addition" 3 42, 4 1 0, S_0x560808804330;
.timescale 0 0;
.port_info 0 /INPUT 4 "A";
.port_info 1 /INPUT 4 "B";
.port_info 2 /INPUT 1 "CarryIN";
.port_info 3 /OUTPUT 4 "Y";
.port_info 4 /OUTPUT 1 "CarryOUT";
.port_info 5 /OUTPUT 1 "overflow";
L_0x5608088424e0 .functor XOR 1, L_0x560808842550, L_0x560808841dc0, C4<0>, C4<0>;
v0x56080882fa20_0 .net "A", 3 0, L_0x56080883fab0; alias, 1 drivers
v0x56080882fb00_0 .net "B", 3 0, L_0x560808842670; 1 drivers
v0x56080882fbe0_0 .net "Carry4", 2 0, L_0x560808841830; 1 drivers
L_0x7f3ea6b4d0a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x56080882fca0_0 .net "CarryIN", 0 0, L_0x7f3ea6b4d0a8; 1 drivers
v0x56080882fd90_0 .net "CarryOUT", 0 0, L_0x560808841dc0; 1 drivers
v0x56080882fe80_0 .net "Y", 3 0, L_0x560808842440; 1 drivers
v0x56080882ff40_0 .net *"_ivl_39", 0 0, L_0x560808842550; 1 drivers
v0x560808830020_0 .net "overflow", 0 0, L_0x5608088424e0; alias, 1 drivers
L_0x560808840590 .part L_0x56080883fab0, 0, 1;
L_0x5608088406c0 .part L_0x560808842670, 0, 1;
L_0x560808840bf0 .part L_0x56080883fab0, 1, 1;
L_0x560808840db0 .part L_0x560808842670, 1, 1;
L_0x560808840ee0 .part L_0x560808841830, 0, 1;
L_0x560808841410 .part L_0x56080883fab0, 2, 1;
L_0x560808841580 .part L_0x560808842670, 2, 1;
L_0x5608088416b0 .part L_0x560808841830, 1, 1;
L_0x560808841830 .concat8 [ 1 1 1 0], L_0x560808840520, L_0x560808840b60, L_0x560808841380;
L_0x560808841ec0 .part L_0x56080883fab0, 3, 1;
L_0x560808842050 .part L_0x560808842670, 3, 1;
L_0x560808842210 .part L_0x560808841830, 2, 1;
L_0x560808842440 .concat8 [ 1 1 1 1], L_0x560808840420, L_0x560808840a80, L_0x5608088412a0, L_0x560808841ce0;
L_0x560808842550 .part L_0x560808841830, 2, 1;
S_0x56080882a5b0 .scope module, "f0" "fulladder" 4 11, 5 1 0, S_0x56080882a310;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x560808840520 .functor OR 1, L_0x560808840100, L_0x5608088402d0, C4<0>, C4<0>;
v0x56080882b430_0 .net "A", 0 0, L_0x560808840590; 1 drivers
v0x56080882b4f0_0 .net "B", 0 0, L_0x5608088406c0; 1 drivers
v0x56080882b5c0_0 .net "Carry", 0 0, L_0x7f3ea6b4d0a8; alias, 1 drivers
v0x56080882b6c0_0 .net "CarryO", 0 0, L_0x560808840520; 1 drivers
v0x56080882b760_0 .net "Sum", 0 0, L_0x560808840420; 1 drivers
v0x56080882b850_0 .net "and1", 0 0, L_0x560808840100; 1 drivers
v0x56080882b920_0 .net "and2", 0 0, L_0x5608088402d0; 1 drivers
v0x56080882b9f0_0 .net "xor1", 0 0, L_0x560808840260; 1 drivers
S_0x56080882a790 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x56080882a5b0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808840100 .functor AND 1, L_0x560808840590, L_0x5608088406c0, C4<1>, C4<1>;
L_0x560808840260 .functor XOR 1, L_0x560808840590, L_0x5608088406c0, C4<0>, C4<0>;
v0x56080882aa30_0 .net "A", 0 0, L_0x560808840590; alias, 1 drivers
v0x56080882ab10_0 .net "B", 0 0, L_0x5608088406c0; alias, 1 drivers
v0x56080882abd0_0 .net "Carry", 0 0, L_0x560808840100; alias, 1 drivers
v0x56080882aca0_0 .net "Sum", 0 0, L_0x560808840260; alias, 1 drivers
S_0x56080882ae10 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x56080882a5b0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x5608088402d0 .functor AND 1, L_0x560808840260, L_0x7f3ea6b4d0a8, C4<1>, C4<1>;
L_0x560808840420 .functor XOR 1, L_0x560808840260, L_0x7f3ea6b4d0a8, C4<0>, C4<0>;
v0x56080882b080_0 .net "A", 0 0, L_0x560808840260; alias, 1 drivers
v0x56080882b150_0 .net "B", 0 0, L_0x7f3ea6b4d0a8; alias, 1 drivers
v0x56080882b1f0_0 .net "Carry", 0 0, L_0x5608088402d0; alias, 1 drivers
v0x56080882b2c0_0 .net "Sum", 0 0, L_0x560808840420; alias, 1 drivers
S_0x56080882bae0 .scope module, "f1" "fulladder" 4 12, 5 1 0, S_0x56080882a310;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x560808840b60 .functor OR 1, L_0x5608088407f0, L_0x5608088408f0, C4<0>, C4<0>;
v0x56080882c940_0 .net "A", 0 0, L_0x560808840bf0; 1 drivers
v0x56080882ca00_0 .net "B", 0 0, L_0x560808840db0; 1 drivers
v0x56080882cad0_0 .net "Carry", 0 0, L_0x560808840ee0; 1 drivers
v0x56080882cbd0_0 .net "CarryO", 0 0, L_0x560808840b60; 1 drivers
v0x56080882cc70_0 .net "Sum", 0 0, L_0x560808840a80; 1 drivers
v0x56080882cd60_0 .net "and1", 0 0, L_0x5608088407f0; 1 drivers
v0x56080882ce30_0 .net "and2", 0 0, L_0x5608088408f0; 1 drivers
v0x56080882cf00_0 .net "xor1", 0 0, L_0x560808840860; 1 drivers
S_0x56080882bcc0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x56080882bae0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x5608088407f0 .functor AND 1, L_0x560808840bf0, L_0x560808840db0, C4<1>, C4<1>;
L_0x560808840860 .functor XOR 1, L_0x560808840bf0, L_0x560808840db0, C4<0>, C4<0>;
v0x56080882bf40_0 .net "A", 0 0, L_0x560808840bf0; alias, 1 drivers
v0x56080882c020_0 .net "B", 0 0, L_0x560808840db0; alias, 1 drivers
v0x56080882c0e0_0 .net "Carry", 0 0, L_0x5608088407f0; alias, 1 drivers
v0x56080882c1b0_0 .net "Sum", 0 0, L_0x560808840860; alias, 1 drivers
S_0x56080882c320 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x56080882bae0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x5608088408f0 .functor AND 1, L_0x560808840860, L_0x560808840ee0, C4<1>, C4<1>;
L_0x560808840a80 .functor XOR 1, L_0x560808840860, L_0x560808840ee0, C4<0>, C4<0>;
v0x56080882c590_0 .net "A", 0 0, L_0x560808840860; alias, 1 drivers
v0x56080882c660_0 .net "B", 0 0, L_0x560808840ee0; alias, 1 drivers
v0x56080882c700_0 .net "Carry", 0 0, L_0x5608088408f0; alias, 1 drivers
v0x56080882c7d0_0 .net "Sum", 0 0, L_0x560808840a80; alias, 1 drivers
S_0x56080882cff0 .scope module, "f2" "fulladder" 4 13, 5 1 0, S_0x56080882a310;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x560808841380 .functor OR 1, L_0x560808841010, L_0x560808841110, C4<0>, C4<0>;
v0x56080882de60_0 .net "A", 0 0, L_0x560808841410; 1 drivers
v0x56080882df20_0 .net "B", 0 0, L_0x560808841580; 1 drivers
v0x56080882dff0_0 .net "Carry", 0 0, L_0x5608088416b0; 1 drivers
v0x56080882e0f0_0 .net "CarryO", 0 0, L_0x560808841380; 1 drivers
v0x56080882e190_0 .net "Sum", 0 0, L_0x5608088412a0; 1 drivers
v0x56080882e280_0 .net "and1", 0 0, L_0x560808841010; 1 drivers
v0x56080882e350_0 .net "and2", 0 0, L_0x560808841110; 1 drivers
v0x56080882e420_0 .net "xor1", 0 0, L_0x560808841080; 1 drivers
S_0x56080882d200 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x56080882cff0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808841010 .functor AND 1, L_0x560808841410, L_0x560808841580, C4<1>, C4<1>;
L_0x560808841080 .functor XOR 1, L_0x560808841410, L_0x560808841580, C4<0>, C4<0>;
v0x56080882d480_0 .net "A", 0 0, L_0x560808841410; alias, 1 drivers
v0x56080882d540_0 .net "B", 0 0, L_0x560808841580; alias, 1 drivers
v0x56080882d600_0 .net "Carry", 0 0, L_0x560808841010; alias, 1 drivers
v0x56080882d6d0_0 .net "Sum", 0 0, L_0x560808841080; alias, 1 drivers
S_0x56080882d840 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x56080882cff0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808841110 .functor AND 1, L_0x560808841080, L_0x5608088416b0, C4<1>, C4<1>;
L_0x5608088412a0 .functor XOR 1, L_0x560808841080, L_0x5608088416b0, C4<0>, C4<0>;
v0x56080882dab0_0 .net "A", 0 0, L_0x560808841080; alias, 1 drivers
v0x56080882db80_0 .net "B", 0 0, L_0x5608088416b0; alias, 1 drivers
v0x56080882dc20_0 .net "Carry", 0 0, L_0x560808841110; alias, 1 drivers
v0x56080882dcf0_0 .net "Sum", 0 0, L_0x5608088412a0; alias, 1 drivers
S_0x56080882e510 .scope module, "f3" "fulladder" 4 14, 5 1 0, S_0x56080882a310;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x560808841dc0 .functor OR 1, L_0x560808841920, L_0x560808841b50, C4<0>, C4<0>;
v0x56080882f370_0 .net "A", 0 0, L_0x560808841ec0; 1 drivers
v0x56080882f430_0 .net "B", 0 0, L_0x560808842050; 1 drivers
v0x56080882f500_0 .net "Carry", 0 0, L_0x560808842210; 1 drivers
v0x56080882f600_0 .net "CarryO", 0 0, L_0x560808841dc0; alias, 1 drivers
v0x56080882f6a0_0 .net "Sum", 0 0, L_0x560808841ce0; 1 drivers
v0x56080882f790_0 .net "and1", 0 0, L_0x560808841920; 1 drivers
v0x56080882f860_0 .net "and2", 0 0, L_0x560808841b50; 1 drivers
v0x56080882f930_0 .net "xor1", 0 0, L_0x560808841ac0; 1 drivers
S_0x56080882e6f0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x56080882e510;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808841920 .functor AND 1, L_0x560808841ec0, L_0x560808842050, C4<1>, C4<1>;
L_0x560808841ac0 .functor XOR 1, L_0x560808841ec0, L_0x560808842050, C4<0>, C4<0>;
v0x56080882e970_0 .net "A", 0 0, L_0x560808841ec0; alias, 1 drivers
v0x56080882ea50_0 .net "B", 0 0, L_0x560808842050; alias, 1 drivers
v0x56080882eb10_0 .net "Carry", 0 0, L_0x560808841920; alias, 1 drivers
v0x56080882ebe0_0 .net "Sum", 0 0, L_0x560808841ac0; alias, 1 drivers
S_0x56080882ed50 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x56080882e510;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808841b50 .functor AND 1, L_0x560808841ac0, L_0x560808842210, C4<1>, C4<1>;
L_0x560808841ce0 .functor XOR 1, L_0x560808841ac0, L_0x560808842210, C4<0>, C4<0>;
v0x56080882efc0_0 .net "A", 0 0, L_0x560808841ac0; alias, 1 drivers
v0x56080882f090_0 .net "B", 0 0, L_0x560808842210; alias, 1 drivers
v0x56080882f130_0 .net "Carry", 0 0, L_0x560808841b50; alias, 1 drivers
v0x56080882f200_0 .net "Sum", 0 0, L_0x560808841ce0; alias, 1 drivers
S_0x5608088301a0 .scope module, "add2" "addition" 3 58, 4 1 0, S_0x560808804330;
.timescale 0 0;
.port_info 0 /INPUT 4 "A";
.port_info 1 /INPUT 4 "B";
.port_info 2 /INPUT 1 "CarryIN";
.port_info 3 /OUTPUT 4 "Y";
.port_info 4 /OUTPUT 1 "CarryOUT";
.port_info 5 /OUTPUT 1 "overflow";
L_0x560808845a10 .functor XOR 1, L_0x560808845a80, L_0x560808845330, C4<0>, C4<0>;
v0x560808835ac0_0 .net "A", 3 0, L_0x560808842da0; alias, 1 drivers
v0x560808835ba0_0 .net "B", 3 0, L_0x560808845ba0; 1 drivers
v0x560808835c80_0 .net "Carry4", 2 0, L_0x560808844e60; 1 drivers
L_0x7f3ea6b4d0f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x560808835d40_0 .net "CarryIN", 0 0, L_0x7f3ea6b4d0f0; 1 drivers
v0x560808835e30_0 .net "CarryOUT", 0 0, L_0x560808845330; 1 drivers
v0x560808835f20_0 .net "Y", 3 0, L_0x560808845970; 1 drivers
v0x560808835fe0_0 .net *"_ivl_39", 0 0, L_0x560808845a80; 1 drivers
v0x5608088360c0_0 .net "overflow", 0 0, L_0x560808845a10; alias, 1 drivers
L_0x560808843e40 .part L_0x560808842da0, 0, 1;
L_0x560808843f70 .part L_0x560808845ba0, 0, 1;
L_0x560808844360 .part L_0x560808842da0, 1, 1;
L_0x560808844520 .part L_0x560808845ba0, 1, 1;
L_0x560808844650 .part L_0x560808844e60, 0, 1;
L_0x560808844a40 .part L_0x560808842da0, 2, 1;
L_0x560808844bb0 .part L_0x560808845ba0, 2, 1;
L_0x560808844ce0 .part L_0x560808844e60, 1, 1;
L_0x560808844e60 .concat8 [ 1 1 1 0], L_0x560808843dd0, L_0x5608088442f0, L_0x5608088449d0;
L_0x5608088453f0 .part L_0x560808842da0, 3, 1;
L_0x560808845580 .part L_0x560808845ba0, 3, 1;
L_0x560808845740 .part L_0x560808844e60, 2, 1;
L_0x560808845970 .concat8 [ 1 1 1 1], L_0x560808843cd0, L_0x560808844280, L_0x560808844960, L_0x560808845270;
L_0x560808845a80 .part L_0x560808844e60, 2, 1;
S_0x560808830420 .scope module, "f0" "fulladder" 4 11, 5 1 0, S_0x5608088301a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x560808843dd0 .functor OR 1, L_0x5608088439b0, L_0x560808843b80, C4<0>, C4<0>;
v0x560808831350_0 .net "A", 0 0, L_0x560808843e40; 1 drivers
v0x560808831410_0 .net "B", 0 0, L_0x560808843f70; 1 drivers
v0x5608088314e0_0 .net "Carry", 0 0, L_0x7f3ea6b4d0f0; alias, 1 drivers
v0x5608088315e0_0 .net "CarryO", 0 0, L_0x560808843dd0; 1 drivers
v0x560808831680_0 .net "Sum", 0 0, L_0x560808843cd0; 1 drivers
v0x560808831770_0 .net "and1", 0 0, L_0x5608088439b0; 1 drivers
v0x560808831840_0 .net "and2", 0 0, L_0x560808843b80; 1 drivers
v0x560808831910_0 .net "xor1", 0 0, L_0x560808843b10; 1 drivers
S_0x5608088306b0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808830420;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x5608088439b0 .functor AND 1, L_0x560808843e40, L_0x560808843f70, C4<1>, C4<1>;
L_0x560808843b10 .functor XOR 1, L_0x560808843e40, L_0x560808843f70, C4<0>, C4<0>;
v0x560808830950_0 .net "A", 0 0, L_0x560808843e40; alias, 1 drivers
v0x560808830a30_0 .net "B", 0 0, L_0x560808843f70; alias, 1 drivers
v0x560808830af0_0 .net "Carry", 0 0, L_0x5608088439b0; alias, 1 drivers
v0x560808830bc0_0 .net "Sum", 0 0, L_0x560808843b10; alias, 1 drivers
S_0x560808830d30 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808830420;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808843b80 .functor AND 1, L_0x560808843b10, L_0x7f3ea6b4d0f0, C4<1>, C4<1>;
L_0x560808843cd0 .functor XOR 1, L_0x560808843b10, L_0x7f3ea6b4d0f0, C4<0>, C4<0>;
v0x560808830fa0_0 .net "A", 0 0, L_0x560808843b10; alias, 1 drivers
v0x560808831070_0 .net "B", 0 0, L_0x7f3ea6b4d0f0; alias, 1 drivers
v0x560808831110_0 .net "Carry", 0 0, L_0x560808843b80; alias, 1 drivers
v0x5608088311e0_0 .net "Sum", 0 0, L_0x560808843cd0; alias, 1 drivers
S_0x560808831a00 .scope module, "f1" "fulladder" 4 12, 5 1 0, S_0x5608088301a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x5608088442f0 .functor OR 1, L_0x5608088440a0, L_0x560808844180, C4<0>, C4<0>;
v0x5608088328e0_0 .net "A", 0 0, L_0x560808844360; 1 drivers
v0x5608088329a0_0 .net "B", 0 0, L_0x560808844520; 1 drivers
v0x560808832a70_0 .net "Carry", 0 0, L_0x560808844650; 1 drivers
v0x560808832b70_0 .net "CarryO", 0 0, L_0x5608088442f0; 1 drivers
v0x560808832c10_0 .net "Sum", 0 0, L_0x560808844280; 1 drivers
v0x560808832d00_0 .net "and1", 0 0, L_0x5608088440a0; 1 drivers
v0x560808832dd0_0 .net "and2", 0 0, L_0x560808844180; 1 drivers
v0x560808832ea0_0 .net "xor1", 0 0, L_0x560808844110; 1 drivers
S_0x560808831c60 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808831a00;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x5608088440a0 .functor AND 1, L_0x560808844360, L_0x560808844520, C4<1>, C4<1>;
L_0x560808844110 .functor XOR 1, L_0x560808844360, L_0x560808844520, C4<0>, C4<0>;
v0x560808831ee0_0 .net "A", 0 0, L_0x560808844360; alias, 1 drivers
v0x560808831fc0_0 .net "B", 0 0, L_0x560808844520; alias, 1 drivers
v0x560808832080_0 .net "Carry", 0 0, L_0x5608088440a0; alias, 1 drivers
v0x560808832150_0 .net "Sum", 0 0, L_0x560808844110; alias, 1 drivers
S_0x5608088322c0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808831a00;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808844180 .functor AND 1, L_0x560808844110, L_0x560808844650, C4<1>, C4<1>;
L_0x560808844280 .functor XOR 1, L_0x560808844110, L_0x560808844650, C4<0>, C4<0>;
v0x560808832530_0 .net "A", 0 0, L_0x560808844110; alias, 1 drivers
v0x560808832600_0 .net "B", 0 0, L_0x560808844650; alias, 1 drivers
v0x5608088326a0_0 .net "Carry", 0 0, L_0x560808844180; alias, 1 drivers
v0x560808832770_0 .net "Sum", 0 0, L_0x560808844280; alias, 1 drivers
S_0x560808832f90 .scope module, "f2" "fulladder" 4 13, 5 1 0, S_0x5608088301a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x5608088449d0 .functor OR 1, L_0x560808844780, L_0x560808844860, C4<0>, C4<0>;
v0x560808833e80_0 .net "A", 0 0, L_0x560808844a40; 1 drivers
v0x560808833f40_0 .net "B", 0 0, L_0x560808844bb0; 1 drivers
v0x560808834010_0 .net "Carry", 0 0, L_0x560808844ce0; 1 drivers
v0x560808834110_0 .net "CarryO", 0 0, L_0x5608088449d0; 1 drivers
v0x5608088341b0_0 .net "Sum", 0 0, L_0x560808844960; 1 drivers
v0x5608088342a0_0 .net "and1", 0 0, L_0x560808844780; 1 drivers
v0x560808834370_0 .net "and2", 0 0, L_0x560808844860; 1 drivers
v0x560808834440_0 .net "xor1", 0 0, L_0x5608088447f0; 1 drivers
S_0x560808833220 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808832f90;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808844780 .functor AND 1, L_0x560808844a40, L_0x560808844bb0, C4<1>, C4<1>;
L_0x5608088447f0 .functor XOR 1, L_0x560808844a40, L_0x560808844bb0, C4<0>, C4<0>;
v0x5608088334a0_0 .net "A", 0 0, L_0x560808844a40; alias, 1 drivers
v0x560808833560_0 .net "B", 0 0, L_0x560808844bb0; alias, 1 drivers
v0x560808833620_0 .net "Carry", 0 0, L_0x560808844780; alias, 1 drivers
v0x5608088336f0_0 .net "Sum", 0 0, L_0x5608088447f0; alias, 1 drivers
S_0x560808833860 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808832f90;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808844860 .functor AND 1, L_0x5608088447f0, L_0x560808844ce0, C4<1>, C4<1>;
L_0x560808844960 .functor XOR 1, L_0x5608088447f0, L_0x560808844ce0, C4<0>, C4<0>;
v0x560808833ad0_0 .net "A", 0 0, L_0x5608088447f0; alias, 1 drivers
v0x560808833ba0_0 .net "B", 0 0, L_0x560808844ce0; alias, 1 drivers
v0x560808833c40_0 .net "Carry", 0 0, L_0x560808844860; alias, 1 drivers
v0x560808833d10_0 .net "Sum", 0 0, L_0x560808844960; alias, 1 drivers
S_0x560808834530 .scope module, "f3" "fulladder" 4 14, 5 1 0, S_0x5608088301a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Carry";
.port_info 3 /OUTPUT 1 "Sum";
.port_info 4 /OUTPUT 1 "CarryO";
L_0x560808845330 .functor OR 1, L_0x560808844f50, L_0x560808845120, C4<0>, C4<0>;
v0x560808835410_0 .net "A", 0 0, L_0x5608088453f0; 1 drivers
v0x5608088354d0_0 .net "B", 0 0, L_0x560808845580; 1 drivers
v0x5608088355a0_0 .net "Carry", 0 0, L_0x560808845740; 1 drivers
v0x5608088356a0_0 .net "CarryO", 0 0, L_0x560808845330; alias, 1 drivers
v0x560808835740_0 .net "Sum", 0 0, L_0x560808845270; 1 drivers
v0x560808835830_0 .net "and1", 0 0, L_0x560808844f50; 1 drivers
v0x560808835900_0 .net "and2", 0 0, L_0x560808845120; 1 drivers
v0x5608088359d0_0 .net "xor1", 0 0, L_0x5608088450b0; 1 drivers
S_0x560808834790 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808834530;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808844f50 .functor AND 1, L_0x5608088453f0, L_0x560808845580, C4<1>, C4<1>;
L_0x5608088450b0 .functor XOR 1, L_0x5608088453f0, L_0x560808845580, C4<0>, C4<0>;
v0x560808834a10_0 .net "A", 0 0, L_0x5608088453f0; alias, 1 drivers
v0x560808834af0_0 .net "B", 0 0, L_0x560808845580; alias, 1 drivers
v0x560808834bb0_0 .net "Carry", 0 0, L_0x560808844f50; alias, 1 drivers
v0x560808834c80_0 .net "Sum", 0 0, L_0x5608088450b0; alias, 1 drivers
S_0x560808834df0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808834530;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "Sum";
.port_info 3 /OUTPUT 1 "Carry";
L_0x560808845120 .functor AND 1, L_0x5608088450b0, L_0x560808845740, C4<1>, C4<1>;
L_0x560808845270 .functor XOR 1, L_0x5608088450b0, L_0x560808845740, C4<0>, C4<0>;
v0x560808835060_0 .net "A", 0 0, L_0x5608088450b0; alias, 1 drivers
v0x560808835130_0 .net "B", 0 0, L_0x560808845740; alias, 1 drivers
v0x5608088351d0_0 .net "Carry", 0 0, L_0x560808845120; alias, 1 drivers
v0x5608088352a0_0 .net "Sum", 0 0, L_0x560808845270; alias, 1 drivers
.scope S_0x560808805dd0;
T_0 ;
%vpi_call 2 13 "$dumpfile", "mult.vcd" {0 0 0};
%vpi_call 2 14 "$dumpvars" {0 0 0};
%pushi/vec4 8, 0, 4;
%store/vec4 v0x56080883b1b0_0, 0, 4;
%pushi/vec4 8, 0, 4;
%store/vec4 v0x56080883b2a0_0, 0, 4;
%delay 5, 0;
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 7;
"N/A";
"<interactive>";
"multTB.v";
"multiplier.v";
"addition.v";
"fulladder.v";
"halfadder.v";

449
tangTest/mult.vcd Normal file
View File

@ -0,0 +1,449 @@
$date
Sun Jan 19 14:35:11 2025
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module multTB $end
$var wire 8 ! Y [7:0] $end
$var reg 4 " A [3:0] $end
$var reg 4 # B [3:0] $end
$scope module uut $end
$var wire 4 $ A [3:0] $end
$var wire 4 % B [3:0] $end
$var wire 1 & overflow2 $end
$var wire 1 ' overflow1 $end
$var wire 1 ( overflow0 $end
$var wire 4 ) b0 [3:0] $end
$var wire 4 * a2 [3:0] $end
$var wire 4 + a1 [3:0] $end
$var wire 4 , a0 [3:0] $end
$var wire 8 - Y [7:0] $end
$var wire 5 . S2 [4:0] $end
$var wire 5 / S1 [4:0] $end
$var wire 5 0 S0 [4:0] $end
$scope module add0 $end
$var wire 4 1 A [3:0] $end
$var wire 4 2 B [3:0] $end
$var wire 1 3 CarryIN $end
$var wire 1 ( overflow $end
$var wire 4 4 Y [3:0] $end
$var wire 1 5 CarryOUT $end
$var wire 3 6 Carry4 [2:0] $end
$scope module f0 $end
$var wire 1 7 A $end
$var wire 1 8 B $end
$var wire 1 3 Carry $end
$var wire 1 9 CarryO $end
$var wire 1 : xor1 $end
$var wire 1 ; and2 $end
$var wire 1 < and1 $end
$var wire 1 = Sum $end
$scope module h1 $end
$var wire 1 7 A $end
$var wire 1 8 B $end
$var wire 1 < Carry $end
$var wire 1 : Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 : A $end
$var wire 1 3 B $end
$var wire 1 ; Carry $end
$var wire 1 = Sum $end
$upscope $end
$upscope $end
$scope module f1 $end
$var wire 1 > A $end
$var wire 1 ? B $end
$var wire 1 @ Carry $end
$var wire 1 A CarryO $end
$var wire 1 B xor1 $end
$var wire 1 C and2 $end
$var wire 1 D and1 $end
$var wire 1 E Sum $end
$scope module h1 $end
$var wire 1 > A $end
$var wire 1 ? B $end
$var wire 1 D Carry $end
$var wire 1 B Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 B A $end
$var wire 1 @ B $end
$var wire 1 C Carry $end
$var wire 1 E Sum $end
$upscope $end
$upscope $end
$scope module f2 $end
$var wire 1 F A $end
$var wire 1 G B $end
$var wire 1 H Carry $end
$var wire 1 I CarryO $end
$var wire 1 J xor1 $end
$var wire 1 K and2 $end
$var wire 1 L and1 $end
$var wire 1 M Sum $end
$scope module h1 $end
$var wire 1 F A $end
$var wire 1 G B $end
$var wire 1 L Carry $end
$var wire 1 J Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 J A $end
$var wire 1 H B $end
$var wire 1 K Carry $end
$var wire 1 M Sum $end
$upscope $end
$upscope $end
$scope module f3 $end
$var wire 1 N A $end
$var wire 1 O B $end
$var wire 1 P Carry $end
$var wire 1 5 CarryO $end
$var wire 1 Q xor1 $end
$var wire 1 R and2 $end
$var wire 1 S and1 $end
$var wire 1 T Sum $end
$scope module h1 $end
$var wire 1 N A $end
$var wire 1 O B $end
$var wire 1 S Carry $end
$var wire 1 Q Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 Q A $end
$var wire 1 P B $end
$var wire 1 R Carry $end
$var wire 1 T Sum $end
$upscope $end
$upscope $end
$upscope $end
$scope module add1 $end
$var wire 4 U A [3:0] $end
$var wire 4 V B [3:0] $end
$var wire 1 W CarryIN $end
$var wire 1 ' overflow $end
$var wire 4 X Y [3:0] $end
$var wire 1 Y CarryOUT $end
$var wire 3 Z Carry4 [2:0] $end
$scope module f0 $end
$var wire 1 [ A $end
$var wire 1 \ B $end
$var wire 1 W Carry $end
$var wire 1 ] CarryO $end
$var wire 1 ^ xor1 $end
$var wire 1 _ and2 $end
$var wire 1 ` and1 $end
$var wire 1 a Sum $end
$scope module h1 $end
$var wire 1 [ A $end
$var wire 1 \ B $end
$var wire 1 ` Carry $end
$var wire 1 ^ Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 ^ A $end
$var wire 1 W B $end
$var wire 1 _ Carry $end
$var wire 1 a Sum $end
$upscope $end
$upscope $end
$scope module f1 $end
$var wire 1 b A $end
$var wire 1 c B $end
$var wire 1 d Carry $end
$var wire 1 e CarryO $end
$var wire 1 f xor1 $end
$var wire 1 g and2 $end
$var wire 1 h and1 $end
$var wire 1 i Sum $end
$scope module h1 $end
$var wire 1 b A $end
$var wire 1 c B $end
$var wire 1 h Carry $end
$var wire 1 f Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 f A $end
$var wire 1 d B $end
$var wire 1 g Carry $end
$var wire 1 i Sum $end
$upscope $end
$upscope $end
$scope module f2 $end
$var wire 1 j A $end
$var wire 1 k B $end
$var wire 1 l Carry $end
$var wire 1 m CarryO $end
$var wire 1 n xor1 $end
$var wire 1 o and2 $end
$var wire 1 p and1 $end
$var wire 1 q Sum $end
$scope module h1 $end
$var wire 1 j A $end
$var wire 1 k B $end
$var wire 1 p Carry $end
$var wire 1 n Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 n A $end
$var wire 1 l B $end
$var wire 1 o Carry $end
$var wire 1 q Sum $end
$upscope $end
$upscope $end
$scope module f3 $end
$var wire 1 r A $end
$var wire 1 s B $end
$var wire 1 t Carry $end
$var wire 1 Y CarryO $end
$var wire 1 u xor1 $end
$var wire 1 v and2 $end
$var wire 1 w and1 $end
$var wire 1 x Sum $end
$scope module h1 $end
$var wire 1 r A $end
$var wire 1 s B $end
$var wire 1 w Carry $end
$var wire 1 u Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 u A $end
$var wire 1 t B $end
$var wire 1 v Carry $end
$var wire 1 x Sum $end
$upscope $end
$upscope $end
$upscope $end
$scope module add2 $end
$var wire 4 y A [3:0] $end
$var wire 4 z B [3:0] $end
$var wire 1 { CarryIN $end
$var wire 1 & overflow $end
$var wire 4 | Y [3:0] $end
$var wire 1 } CarryOUT $end
$var wire 3 ~ Carry4 [2:0] $end
$scope module f0 $end
$var wire 1 !" A $end
$var wire 1 "" B $end
$var wire 1 { Carry $end
$var wire 1 #" CarryO $end
$var wire 1 $" xor1 $end
$var wire 1 %" and2 $end
$var wire 1 &" and1 $end
$var wire 1 '" Sum $end
$scope module h1 $end
$var wire 1 !" A $end
$var wire 1 "" B $end
$var wire 1 &" Carry $end
$var wire 1 $" Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 $" A $end
$var wire 1 { B $end
$var wire 1 %" Carry $end
$var wire 1 '" Sum $end
$upscope $end
$upscope $end
$scope module f1 $end
$var wire 1 (" A $end
$var wire 1 )" B $end
$var wire 1 *" Carry $end
$var wire 1 +" CarryO $end
$var wire 1 ," xor1 $end
$var wire 1 -" and2 $end
$var wire 1 ." and1 $end
$var wire 1 /" Sum $end
$scope module h1 $end
$var wire 1 (" A $end
$var wire 1 )" B $end
$var wire 1 ." Carry $end
$var wire 1 ," Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 ," A $end
$var wire 1 *" B $end
$var wire 1 -" Carry $end
$var wire 1 /" Sum $end
$upscope $end
$upscope $end
$scope module f2 $end
$var wire 1 0" A $end
$var wire 1 1" B $end
$var wire 1 2" Carry $end
$var wire 1 3" CarryO $end
$var wire 1 4" xor1 $end
$var wire 1 5" and2 $end
$var wire 1 6" and1 $end
$var wire 1 7" Sum $end
$scope module h1 $end
$var wire 1 0" A $end
$var wire 1 1" B $end
$var wire 1 6" Carry $end
$var wire 1 4" Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 4" A $end
$var wire 1 2" B $end
$var wire 1 5" Carry $end
$var wire 1 7" Sum $end
$upscope $end
$upscope $end
$scope module f3 $end
$var wire 1 8" A $end
$var wire 1 9" B $end
$var wire 1 :" Carry $end
$var wire 1 } CarryO $end
$var wire 1 ;" xor1 $end
$var wire 1 <" and2 $end
$var wire 1 =" and1 $end
$var wire 1 >" Sum $end
$scope module h1 $end
$var wire 1 8" A $end
$var wire 1 9" B $end
$var wire 1 =" Carry $end
$var wire 1 ;" Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 ;" A $end
$var wire 1 :" B $end
$var wire 1 <" Carry $end
$var wire 1 >" Sum $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1>"
0="
0<"
1;"
0:"
09"
18"
07"
06"
05"
04"
03"
02"
01"
00"
0/"
0."
0-"
0,"
0+"
0*"
0)"
0("
0'"
0&"
0%"
0$"
0#"
0""
0!"
b0 ~
0}
b1000 |
0{
b0 z
b1000 y
0x
0w
0v
0u
0t
0s
0r
0q
0p
0o
0n
0m
0l
0k
0j
0i
0h
0g
0f
0e
0d
0c
0b
0a
0`
0_
0^
0]
0\
0[
b0 Z
0Y
b0 X
0W
b0 V
b0 U
0T
0S
0R
0Q
0P
0O
0N
0M
0L
0K
0J
0I
0H
0G
0F
0E
0D
0C
0B
0A
0@
0?
0>
0=
0<
0;
0:
09
08
07
b0 6
05
b0 4
03
b0 2
b0 1
b0 0
b0 /
b1000 .
b1000000 -
b0 ,
b0 +
b1000 *
b0 )
0(
0'
0&
b1000 %
b1000 $
b1000 #
b1000 "
b1000000 !
$end
#5

18
tangTest/multTB.v Normal file
View File

@ -0,0 +1,18 @@
module multTB();
reg [3:0] A, B;
wire [7:0] Y;
multiplier uut (
.A(A),
.B(B),
.Y(Y)
);
initial begin
$dumpfile("mult.vcd");
$dumpvars;
A = 4'b1000; B = 4'b1000; #5;
end
endmodule

0
spartanTest/multiplier.v → tangTest/multiplier.v
View File

0
spartanTest/opCode.v → tangTest/opCode.v
View File

20
tangTest/selector.v Normal file
View File

@ -0,0 +1,20 @@
module selector (
input [3:0] A,
input [3:0] B,
input [2:0] opCodeA,
input [1:0] select,
input [11:0] ALUY,
output reg [11:0] Y
);
always @(*) begin
case (select)
2'b00: Y = {8'b00000000, A}; // Zero-extend A to 8 bits
2'b01: Y = {8'b00000000, B}; // Zero-extend B to 8 bits
2'b10: Y = {9'b000000000, opCodeA}; // Zero-extend opCodeA to 8 bits
2'b11: Y = ALUY; // Directly assign ALUY
default: Y = ALUY; // Default case for safety
endcase
end
endmodule

0
spartanTest/subtraction.v → tangTest/subtraction.v
View File