kaltinsoy/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

f# fix

Browse Source
This commit is contained in:
k0rrluna
2025-01-23 07:58:44 +03:00
parent 8003e7f253
commit 0f359fa8a4
76 changed files with 2250 additions and 19410 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2220
tangTest/bttn
View File

File diff suppressed because it is too large Load Diff

59
tangTest/bttn.cst
View File

@ -1,59 +0,0 @@
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Physical Constraints file
//Tool Version: V1.9.9.03 Education (64-bit)
//Part Number: GW2A-LV18PG256C8/I7
//Device: GW2A-18
//Device Version: C
//Created Time: Sat 01 18 21:56:09 2025
IO_LOC "Y[11]" B12;
IO_PORT "Y[11]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[10]" B13;
IO_PORT "Y[10]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[9]" B14;
IO_PORT "Y[9]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[8]" D14;
IO_PORT "Y[8]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[7]" J14;
IO_PORT "Y[7]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[6]" M14;
IO_PORT "Y[6]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[5]" T12;
IO_PORT "Y[5]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[4]" T11;
IO_PORT "Y[4]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[3]" P9;
IO_PORT "Y[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[2]" P8;
IO_PORT "Y[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[1]" T7;
IO_PORT "Y[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "Y[0]" P6;
IO_PORT "Y[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "select[1]" A14;
IO_PORT "select[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "select[0]" A15;
IO_PORT "select[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[2]" E8;
IO_PORT "opCodeA[2]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[1]" T4;
IO_PORT "opCodeA[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "opCodeA[0]" T5;
IO_PORT "opCodeA[0]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "B[3]" N8;
IO_PORT "B[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[2]" N7;
IO_PORT "B[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[1]" D11;
IO_PORT "B[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "B[0]" B11;
IO_PORT "B[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[3]" L9;
IO_PORT "A[3]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[2]" E15;
IO_PORT "A[2]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[1]" N6;
IO_PORT "A[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;
IO_LOC "A[0]" A11;
IO_PORT "A[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE BANK_VCCIO=1.8;

10
tangTest/compile.sh Normal file
View File

@ -0,0 +1,10 @@
#!/bin/bash
# Granting execute permissions to this script (one-time setup)
# chmod +x script_name.sh
# Using Icarus Verilog to compile Verilog files for simulation
iverilog -o top top.v topTB.v ALU.v selector.v BinaryToBCD.v arithmeticUnit.v logicUnit.v multiplier.v opCode.v addition.v dabble.v subtraction.v fulladder.v fullsubtraction.v halfadder.v halfsubtraction.v
# Running the simulation
vvp top

2220
tangTest/top Normal file
View File

File diff suppressed because it is too large Load Diff

2
tangTest/bttn.v → tangTest/top.v
View File

@ -1,4 +1,4 @@
module bttn (
module top (
input [3:0] A, B,
input [2:0] opCodeA,
input [1:0] select,

4
tangTest/bttn.vcd → tangTest/top.vcd
View File

@ -1,5 +1,5 @@
$date
Mon Jan 20 01:37:42 2025
Thu Jan 23 05:37:04 2025
$end
$version
Icarus Verilog
@ -7,7 +7,7 @@ $end
$timescale
1s
$end
$scope module bttnTB $end
$scope module topTB $end
$var wire 2 ! led [1:0] $end
$var wire 12 " Y [11:0] $end
$var reg 4 # A [3:0] $end

6
tangTest/bttnTB.v → tangTest/topTB.v
View File

@ -1,4 +1,4 @@
module bttnTB();
module topTB();
reg [3:0] A,B;
reg [2:0] opCodeA;
@ -6,7 +6,7 @@ reg [1:0] select;
wire [1:0] led;
wire [11:0] Y;
bttn uut (
top uut (
.A(A),
.B(B),
.opCodeA(opCodeA),
@ -16,7 +16,7 @@ bttn uut (
);
initial begin
$dumpfile("bttn.vcd");
$dumpfile("top.vcd");
$dumpvars;
A = 4'b1111; B = 4'b1111; opCodeA = 3'b000; select = 2'b01; #5;
A = 4'b0000; B = 4'b1111; opCodeA = 3'b001; select = 2'b01; #5;