kaltinsoy/verilog
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f# fix

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k0rrluna
2025-01-23 07:58:44 +03:00
parent 8003e7f253
commit 0f359fa8a4
76 changed files with 2250 additions and 19410 deletions
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4
gowin/bttn/bttn.gprj
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@ -9,7 +9,6 @@
<File path="src/BinaryToBCD.v" type="file.verilog" enable="1"/>
<File path="src/addition.v" type="file.verilog" enable="1"/>
<File path="src/arithmeticUnit.v" type="file.verilog" enable="1"/>
<File path="src/bttn.v" type="file.verilog" enable="1"/>
<File path="src/dabble.v" type="file.verilog" enable="1"/>
<File path="src/fulladder.v" type="file.verilog" enable="1"/>
<File path="src/fullsubtraction.v" type="file.verilog" enable="1"/>
@ -20,6 +19,7 @@
<File path="src/opCode.v" type="file.verilog" enable="1"/>
<File path="src/selector.v" type="file.verilog" enable="1"/>
<File path="src/subtraction.v" type="file.verilog" enable="1"/>
<File path="src/bttn.cst" type="file.cst" enable="1"/>
<File path="src/top.v" type="file.verilog" enable="1"/>
<File path="src/top.cst" type="file.cst" enable="1"/>
</FileList>
</Project>