rearrangement

2024-12-01 02:01:08 +03:00
parent 7466f916d3
commit 0237c7bcb2
277 changed files with 56884 additions and 56884 deletions
--- a/iverilog/tobb/lab2/fulladder.v
+++ b/iverilog/tobb/lab2/fulladder.v
@ -0,0 +1,13 @@
+module fullAdder (
+    input A,
+    input B,
+    input Cin,
+    output S,
+    output Cout
+);
+    wire AxB, AnB1, AnB2;
+    halfadder h1(A, B, AxB, AnB2);
+    halfadder h2(AxB, Cin, S, AnB1);
+
+    or o1(Cout, AnB1, AnB2);
+endmodule