132 lines
3.9 KiB
Coq
132 lines
3.9 KiB
Coq
/*
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* PicoSoC - A simple example SoC using PicoRV32
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*
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* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// October 2019, Matthias Koch: Renamed wires
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// December 2020, Bruno Levy: parameterization with freq and bauds
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module buart #(
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parameter FREQ_MHZ = 60,
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parameter BAUDS = 115200
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) (
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input clk,
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input resetq,
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output tx,
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input rx,
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input wr,
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input rd,
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input [7:0] tx_data,
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output [7:0] rx_data,
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output busy,
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output valid
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);
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parameter divider = FREQ_MHZ * 1000000 / BAUDS;
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reg [3:0] recv_state;
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reg [$clog2(divider)-1:0] recv_divcnt; // Counts to divider. Reserve enough bytes !
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reg [7:0] recv_pattern;
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reg [7:0] recv_buf_data;
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reg recv_buf_valid;
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reg [9:0] send_pattern;
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reg send_dummy;
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reg [3:0] send_bitcnt;
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reg [$clog2(divider)-1:0] send_divcnt; // Counts to divider. Reserve enough bytes !
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assign rx_data = recv_buf_data;
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assign valid = recv_buf_valid;
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assign busy = (send_bitcnt || send_dummy);
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always @(posedge clk) begin
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if (!resetq) begin
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recv_state <= 0;
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recv_divcnt <= 0;
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recv_pattern <= 0;
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recv_buf_data <= 0;
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recv_buf_valid <= 0;
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end else begin
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recv_divcnt <= recv_divcnt + 1;
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if (rd) recv_buf_valid <= 0;
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case (recv_state)
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0: begin
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if (!rx)
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recv_state <= 1;
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end
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1: begin
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if (recv_divcnt > divider/2) begin
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recv_state <= 2;
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recv_divcnt <= 0;
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end
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end
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10: begin
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if (recv_divcnt > divider) begin
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recv_buf_data <= recv_pattern;
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recv_buf_valid <= 1;
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recv_state <= 0;
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end
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end
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default: begin
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if (recv_divcnt > divider) begin
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recv_pattern <= {rx, recv_pattern[7:1]};
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recv_state <= recv_state + 1;
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recv_divcnt <= 0;
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end
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end
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endcase
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end
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end
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assign tx = send_pattern[0];
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always @(posedge clk) begin
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send_divcnt <= send_divcnt + 1;
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if (!resetq) begin
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send_pattern <= ~0;
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send_bitcnt <= 0;
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send_divcnt <= 0;
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send_dummy <= 1;
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end else begin
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if (send_dummy && !send_bitcnt) begin
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send_pattern <= ~0;
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send_bitcnt <= 15;
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send_divcnt <= 0;
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send_dummy <= 0;
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end else if (wr && !send_bitcnt) begin
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send_pattern <= {1'b1, tx_data[7:0], 1'b0};
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send_bitcnt <= 10;
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send_divcnt <= 0;
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end else if (send_divcnt > divider && send_bitcnt) begin
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send_pattern <= {1'b1, send_pattern[9:1]};
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send_bitcnt <= send_bitcnt - 1;
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send_divcnt <= 0;
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end
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end
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end
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endmodule
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