96 lines
2.5 KiB
Verilog
96 lines
2.5 KiB
Verilog
// femtorv32, a minimalistic RISC-V RV32I core
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//
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// Bruno Levy, 2020-2021
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//
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// This file: driver for UART (serial over USB)
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// Wrapper around modified Claire Wolf's UART
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`ifdef BENCH
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// If BENCH is define, using a fake UART that displays
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// each sent character.
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module UART(
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input wire clk, // system clock
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input wire rstrb, // read strobe
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input wire wstrb, // write strobe
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input wire sel_dat, // select data reg (rw)
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input wire sel_cntl, // select control reg (r)
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input wire [31:0] wdata, // data to be written
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output wire [31:0] rdata, // data read
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input wire RXD, // UART pins (unused in bench mode)
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output wire TXD,
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output reg brk // goes high one cycle when <ctrl><C> is pressed.
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);
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assign rdata = 32'b0;
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assign TXD = 1'b0;
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always @(posedge clk) begin
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if(sel_dat && wstrb) begin
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if(wdata == 32'd4) begin
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$display("<end of simulation> (EOT sent to UART)");
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$finish();
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end
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$write("%c",wdata[7:0]);
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$fflush(32'h8000_0001);
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end
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end
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endmodule
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`else
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// For some reasons, our 'compressed' version of
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// the UART does not work on the ARTY, there is
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// probably a couple of bugs there...
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`ifdef ARTY
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`include "uart_picosoc.v.orig"
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`else
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`include "uart_picosoc_shrunk.v"
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`endif
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module UART(
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input wire clk, // system clock
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input wire rstrb, // read strobe
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input wire wstrb, // write strobe
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input wire sel_dat, // select data reg (rw)
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input wire sel_cntl, // select control reg (r)
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input wire [31:0] wdata, // data to be written
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output wire [31:0] rdata, // data read
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input wire RXD, // UART pins
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output wire TXD,
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output reg brk // goes high one cycle when <ctrl><C> is pressed.
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);
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wire [7:0] rx_data;
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wire [7:0] tx_data;
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wire serial_tx_busy;
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wire serial_valid;
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buart #(
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.FREQ_MHZ(`NRV_FREQ),
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.BAUDS(115200)
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) the_buart (
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.clk(clk),
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.resetq(!brk),
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.tx(TXD),
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.rx(RXD),
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.tx_data(wdata[7:0]),
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.rx_data(rx_data),
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.busy(serial_tx_busy),
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.valid(serial_valid),
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.wr(sel_dat && wstrb),
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.rd(sel_dat && rstrb)
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);
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assign rdata = sel_dat ? {22'b0, serial_tx_busy, serial_valid, rx_data}
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: sel_cntl ? {22'b0, serial_tx_busy, serial_valid, 8'b0 }
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: 32'b0;
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always @(posedge clk) begin
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brk <= serial_valid && (rx_data == 8'd3);
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end
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endmodule
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`endif
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