43 lines
1.8 KiB
Verilog
43 lines
1.8 KiB
Verilog
// Default femtosoc configuration file for ARTY
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/*** Devices ******************************************************************/
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`define NRV_IO_LEDS // Mapped IO, LEDs D1,D2,D3,D4 (D5 = errors)
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`define NRV_IO_UART // Mapped IO, virtual UART (USB)
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`define NRV_IO_SSD1351 // Mapped IO, 128x128x64K OLED screen
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//`define NRV_IO_MAX7219 // Mapped IO, 8x8 led matrix
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//`define NRV_MAPPED_SPI_FLASH // SPI flash mapped in address space.
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/*** Processor configuration **************************************************/
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`define NRV_FREQ 70 // Frequency in MHz, needs to be a multiple of 5
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// CORE RV32 subset fmax validated-experimental
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//
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//`define NRV_FEMTORV32_QUARK // RV32I fmax = 80-110 MHz
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//`define NRV_FEMTORV32_TACHYON // RV32I fmax = 100-135 MHz
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//`define NRV_FEMTORV32_ELECTRON // RV32IM fmax = 70-80 MHz
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//`define NRV_FEMTORV32_INTERMISSUM // RV32IM, IRQ fmax = 60-80 MHz
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//`define NRV_FEMTORV32_GRACILIS // RV32IMC, IRQ fmax = 60-80 MHz
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`define NRV_FEMTORV32_PETITBATEAU // RV32IMFC, IRQ fmax = 50-80 MHz
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//`define NRV_FEMTORV32_TESTDRIVE
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`define NRV_RESET_ADDR 0 // The address the processor jumps to on reset
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/*** RAM (in bytes, needs to be a multiple of 4)*******************************/
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`define NRV_RAM 65536
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//`define NRV_RAM 262144 // On the ARTY, does not work with more than 64k,
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// I don't know why.
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/*** Advanced devices configuration *******************************************/
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`define NRV_IO_HARDWARE_CONFIG // Hardware config registers mapped in IO-Space
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// (note: firmware libfemtorv32 depends on it)
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/******************************************************************************/
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`define NRV_NEGATIVE_RESET // reset button active low
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`define NRV_CONFIGURED
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