15 lines
158 B
Verilog
15 lines
158 B
Verilog
module mux (
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input [1:0] A,
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input S,
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output Y
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);
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wire and1, and2;
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and a1 (and1, A[0], S);
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and a2 (and2, A[1], ~S);
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or o1 (Y, and1, and2);
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endmodule
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