20 lines
270 B
Verilog
20 lines
270 B
Verilog
module fulladder (
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input in1,
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input in2,
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input carryIn,
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output sum,
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output carryO
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);
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wire xor1, and1, and2;
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xor x1 (xor1, in1, in2);
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xor x2 (sum, xor1, carryIn);
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and a1 (and1, xor1, carryIn);
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and a2 (and2, in1, in2);
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or o1 (carryO, and1, and2);
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endmodule
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