initial

chapter4/pc.vcd

@@ -0,0 +1,201 @@
+$date
+	Mon Aug 18 02:30:00 2025
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module pcTB $end
+$var wire 32 ! pc [31:0] $end
+$var wire 32 " next_pc [31:0] $end
+$var reg 1 # clk $end
+$var reg 1 $ rst $end
+$scope module uut $end
+$var wire 1 # clk $end
+$var wire 1 $ rst $end
+$var reg 32 % next_pc [31:0] $end
+$var reg 32 & pc [31:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$comment Show the parameter values. $end
+$dumpall
+$end
+#0
+$dumpvars
+bx &
+bx %
+1$
+0#
+bx "
+bx !
+$end
+#2
+b0 !
+b0 &
+1#
+#4
+0#
+0$
+#6
+b1 !
+b1 &
+b0 "
+b0 %
+1#
+#8
+0#
+#10
+b10 !
+b10 &
+b1 "
+b1 %
+1#
+#12
+0#
+#14
+b11 !
+b11 &
+b10 "
+b10 %
+1#
+#16
+0#
+#18
+b100 !
+b100 &
+b11 "
+b11 %
+1#
+#20
+0#
+#22
+b101 !
+b101 &
+b100 "
+b100 %
+1#
+#24
+0#
+#26
+b110 !
+b110 &
+b101 "
+b101 %
+1#
+#28
+0#
+#30
+b111 !
+b111 &
+b110 "
+b110 %
+1#
+#32
+0#
+#34
+b1000 !
+b1000 &
+b111 "
+b111 %
+1#
+#36
+0#
+#38
+b1001 !
+b1001 &
+b1000 "
+b1000 %
+1#
+#40
+0#
+#42
+b1010 !
+b1010 &
+b1001 "
+b1001 %
+1#
+#44
+0#
+#46
+b1011 !
+b1011 &
+b1010 "
+b1010 %
+1#
+#48
+0#
+#50
+b1100 !
+b1100 &
+b1011 "
+b1011 %
+1#
+#52
+0#
+#54
+b1101 !
+b1101 &
+b1100 "
+b1100 %
+1#
+#56
+0#
+#58
+b1110 !
+b1110 &
+b1101 "
+b1101 %
+1#
+#60
+0#
+#62
+b1111 !
+b1111 &
+b1110 "
+b1110 %
+1#
+#64
+0#
+#66
+b10000 !
+b10000 &
+b1111 "
+b1111 %
+1#
+#68
+0#
+#70
+b10001 !
+b10001 &
+b10000 "
+b10000 %
+1#
+#72
+0#
+#74
+b10010 !
+b10010 &
+b10001 "
+b10001 %
+1#
+#76
+0#
+#78
+b10011 !
+b10011 &
+b10010 "
+b10010 %
+1#
+#80
+0#
+#82
+b10100 !
+b10100 &
+b10011 "
+b10011 %
+1#
+#84
+0#