202 lines
1.4 KiB
Plaintext
202 lines
1.4 KiB
Plaintext
$date
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Mon Aug 18 02:30:00 2025
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module pcTB $end
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$var wire 32 ! pc [31:0] $end
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$var wire 32 " next_pc [31:0] $end
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$var reg 1 # clk $end
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$var reg 1 $ rst $end
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$scope module uut $end
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$var wire 1 # clk $end
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$var wire 1 $ rst $end
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$var reg 32 % next_pc [31:0] $end
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$var reg 32 & pc [31:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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$comment Show the parameter values. $end
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$dumpall
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$end
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#0
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$dumpvars
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bx &
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bx %
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1$
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0#
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bx "
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bx !
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$end
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#2
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b0 !
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b0 &
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1#
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#4
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0#
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0$
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#6
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b1 !
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b1 &
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b0 "
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b0 %
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1#
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#8
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0#
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#10
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b10 !
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b10 &
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b1 "
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b1 %
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1#
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#12
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0#
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#14
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b11 !
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b11 &
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b10 "
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b10 %
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1#
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#16
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0#
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#18
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b100 !
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b100 &
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b11 "
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b11 %
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1#
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#20
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0#
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#22
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b101 !
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b101 &
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b100 "
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b100 %
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1#
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#24
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0#
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#26
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b110 !
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b110 &
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b101 "
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b101 %
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1#
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#28
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0#
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#30
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b111 !
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b111 &
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b110 "
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b110 %
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1#
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#32
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0#
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#34
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b1000 !
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b1000 &
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b111 "
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b111 %
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1#
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#36
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0#
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#38
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b1001 !
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b1001 &
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b1000 "
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b1000 %
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1#
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#40
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0#
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#42
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b1010 !
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b1010 &
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b1001 "
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b1001 %
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1#
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#44
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0#
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#46
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b1011 !
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b1011 &
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b1010 "
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b1010 %
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1#
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#48
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0#
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#50
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b1100 !
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b1100 &
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b1011 "
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b1011 %
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1#
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#52
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0#
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#54
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b1101 !
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b1101 &
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b1100 "
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b1100 %
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1#
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#56
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0#
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#58
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b1110 !
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b1110 &
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b1101 "
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b1101 %
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1#
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#60
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0#
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#62
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b1111 !
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b1111 &
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b1110 "
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b1110 %
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1#
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#64
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0#
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#66
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b10000 !
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b10000 &
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b1111 "
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b1111 %
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1#
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#68
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0#
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#70
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b10001 !
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b10001 &
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b10000 "
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b10000 %
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1#
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#72
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0#
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#74
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b10010 !
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b10010 &
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b10001 "
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b10001 %
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1#
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#76
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0#
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#78
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b10011 !
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b10011 &
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b10010 "
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b10010 %
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1#
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#80
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0#
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#82
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b10100 !
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b10100 &
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b10011 "
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b10011 %
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1#
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#84
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0#
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