initial commit
This commit is contained in:
130
gowin/ALU/impl/gwsynthesis/ALU.log
Normal file
130
gowin/ALU/impl/gwsynthesis/ALU.log
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GowinSynthesis start
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Running parser ...
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\addition.v'
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\ALU.v'
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||||
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v'
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||||
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v'
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||||
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\dabble.v'
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||||
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\fulladder.v'
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||||
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v'
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||||
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\halfadder.v'
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\halfsubtraction.v'
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||||
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\logicUnit.v'
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||||
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\multiplier.v'
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\opCode.v'
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Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\selector.v'
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||||
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\subtraction.v'
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||||
Analyzing Verilog file 'C:\Users\koray\Documents\gowin\ALU\src\top.v'
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||||
Compiling module 'top'("C:\Users\koray\Documents\gowin\ALU\src\top.v":1)
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Compiling module 'ALU'("C:\Users\koray\Documents\gowin\ALU\src\ALU.v":1)
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Compiling module 'opCode'("C:\Users\koray\Documents\gowin\ALU\src\opCode.v":1)
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Compiling module 'arithmeticUnit'("C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v":1)
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Compiling module 'addition'("C:\Users\koray\Documents\gowin\ALU\src\addition.v":1)
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Compiling module 'fulladder'("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":1)
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Compiling module 'halfadder'("C:\Users\koray\Documents\gowin\ALU\src\halfadder.v":1)
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Compiling module 'subtraction'("C:\Users\koray\Documents\gowin\ALU\src\subtraction.v":1)
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Compiling module 'fullsubtraction'("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":1)
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Compiling module 'halfsubtraction'("C:\Users\koray\Documents\gowin\ALU\src\halfsubtraction.v":1)
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Compiling module 'logicUnit'("C:\Users\koray\Documents\gowin\ALU\src\logicUnit.v":1)
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Compiling module 'multiplier'("C:\Users\koray\Documents\gowin\ALU\src\multiplier.v":1)
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Compiling module 'BinaryToBCD'("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":1)
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Compiling module 'dabble'("C:\Users\koray\Documents\gowin\ALU\src\dabble.v":1)
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Compiling module 'selector'("C:\Users\koray\Documents\gowin\ALU\src\selector.v":1)
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NOTE (EX0101) : Current top module is "top"
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[5%] Running netlist conversion ...
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Running device independent optimization ...
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[10%] Optimizing Phase 0 completed
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[15%] Optimizing Phase 1 completed
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[25%] Optimizing Phase 2 completed
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Running inference ...
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[30%] Inferring Phase 0 completed
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[40%] Inferring Phase 1 completed
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[50%] Inferring Phase 2 completed
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[55%] Inferring Phase 3 completed
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Running technical mapping ...
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[60%] Tech-Mapping Phase 0 completed
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[65%] Tech-Mapping Phase 1 completed
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[75%] Tech-Mapping Phase 2 completed
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[80%] Tech-Mapping Phase 3 completed
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[90%] Tech-Mapping Phase 4 completed
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WARN (NL0002) : The module "ALU" instantiated to "a1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\top.v":13)
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WARN (NL0002) : The module "arithmeticUnit" instantiated to "aU" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\ALU.v":20)
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WARN (NL0002) : The module "addition" instantiated to "a1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v":13)
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WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":11)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":12)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":13)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":14)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "subtraction" instantiated to "s1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v":14)
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WARN (NL0002) : The module "fullsubtraction" instantiated to "f0" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\subtraction.v":11)
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WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":8)
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WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":9)
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WARN (NL0002) : The module "fullsubtraction" instantiated to "f1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\subtraction.v":12)
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WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":8)
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WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":9)
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WARN (NL0002) : The module "fullsubtraction" instantiated to "f2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\subtraction.v":13)
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WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":8)
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WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":9)
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WARN (NL0002) : The module "fullsubtraction" instantiated to "f3" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\subtraction.v":14)
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WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":8)
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WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v":9)
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||||
WARN (NL0002) : The module "BinaryToBCD" instantiated to "btod1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\ALU.v":76)
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WARN (NL0002) : The module "dabble" instantiated to "d1t" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":21)
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WARN (NL0002) : The module "dabble" instantiated to "d2u" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":30)
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WARN (NL0002) : The module "dabble" instantiated to "d3v" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":39)
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WARN (NL0002) : The module "dabble" instantiated to "d4w" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":48)
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WARN (NL0002) : The module "dabble" instantiated to "d5x" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":57)
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WARN (NL0002) : The module "dabble" instantiated to "d6y" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":66)
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WARN (NL0002) : The module "dabble" instantiated to "d7z" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v":75)
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||||
WARN (NL0002) : The module "logicUnit" instantiated to "lU" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\ALU.v":21)
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WARN (NL0002) : The module "multiplier" instantiated to "mU" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\ALU.v":22)
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WARN (NL0002) : The module "addition" instantiated to "add0" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\multiplier.v":33)
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WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":11)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":12)
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WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":13)
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||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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||||
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":14)
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||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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||||
WARN (NL0002) : The module "addition" instantiated to "add1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\multiplier.v":49)
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||||
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":11)
|
||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
|
||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
|
||||
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":12)
|
||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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||||
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":13)
|
||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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||||
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":14)
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||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "addition" instantiated to "add2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\multiplier.v":65)
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WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":11)
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||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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||||
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":12)
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||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":13)
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||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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||||
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\addition.v":14)
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||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":8)
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WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\fulladder.v":9)
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||||
WARN (NL0002) : The module "opCode" instantiated to "opCd" is swept in optimizing("C:\Users\koray\Documents\gowin\ALU\src\ALU.v":18)
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[95%] Generate netlist file "C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg" completed
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[100%] Generate report file "C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU_syn.rpt.html" completed
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GowinSynthesis finish
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35
gowin/ALU/impl/gwsynthesis/ALU.prj
Normal file
35
gowin/ALU/impl/gwsynthesis/ALU.prj
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@ -0,0 +1,35 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||
<!DOCTYPE gowin-synthesis-project>
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||||
<Project>
|
||||
<Version>beta</Version>
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||||
<Device id="GW2A-18" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
|
||||
<FileList>
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||||
<File path="C:\Users\koray\Documents\gowin\ALU\src\addition.v" type="verilog"/>
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||||
<File path="C:\Users\koray\Documents\gowin\ALU\src\ALU.v" type="verilog"/>
|
||||
<File path="C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v" type="verilog"/>
|
||||
<File path="C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v" type="verilog"/>
|
||||
<File path="C:\Users\koray\Documents\gowin\ALU\src\dabble.v" type="verilog"/>
|
||||
<File path="C:\Users\koray\Documents\gowin\ALU\src\fulladder.v" type="verilog"/>
|
||||
<File path="C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v" type="verilog"/>
|
||||
<File path="C:\Users\koray\Documents\gowin\ALU\src\halfadder.v" type="verilog"/>
|
||||
<File path="C:\Users\koray\Documents\gowin\ALU\src\halfsubtraction.v" type="verilog"/>
|
||||
<File path="C:\Users\koray\Documents\gowin\ALU\src\logicUnit.v" type="verilog"/>
|
||||
<File path="C:\Users\koray\Documents\gowin\ALU\src\multiplier.v" type="verilog"/>
|
||||
<File path="C:\Users\koray\Documents\gowin\ALU\src\opCode.v" type="verilog"/>
|
||||
<File path="C:\Users\koray\Documents\gowin\ALU\src\selector.v" type="verilog"/>
|
||||
<File path="C:\Users\koray\Documents\gowin\ALU\src\subtraction.v" type="verilog"/>
|
||||
<File path="C:\Users\koray\Documents\gowin\ALU\src\top.v" type="verilog"/>
|
||||
</FileList>
|
||||
<OptionList>
|
||||
<Option type="disable_insert_pad" value="0"/>
|
||||
<Option type="global_freq" value="100.000"/>
|
||||
<Option type="looplimit" value="2000"/>
|
||||
<Option type="output_file" value="C:\Users\koray\Documents\gowin\ALU\impl\gwsynthesis\ALU.vg"/>
|
||||
<Option type="print_all_synthesis_warning" value="0"/>
|
||||
<Option type="ram_rw_check" value="0"/>
|
||||
<Option type="vcc" value="1.0"/>
|
||||
<Option type="vccx" value="3.3"/>
|
||||
<Option type="verilog_language" value="verilog-2001"/>
|
||||
<Option type="vhdl_language" value="vhdl-1993"/>
|
||||
</OptionList>
|
||||
</Project>
|
||||
1397
gowin/ALU/impl/gwsynthesis/ALU.vg
Normal file
1397
gowin/ALU/impl/gwsynthesis/ALU.vg
Normal file
File diff suppressed because it is too large
Load Diff
185
gowin/ALU/impl/gwsynthesis/ALU_syn.rpt.html
Normal file
185
gowin/ALU/impl/gwsynthesis/ALU_syn.rpt.html
Normal file
@ -0,0 +1,185 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>synthesis Report</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
div#content { margin-left: 350px; margin-right: 30px; }
|
||||
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
|
||||
div#catalog ul { list-style-type: none; }
|
||||
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
|
||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
|
||||
div#catalog a:visited { color: #0084ff; }
|
||||
div#catalog a:hover { color: #fff; background: #0084ff; }
|
||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
||||
h1, h3 { text-align: center; }
|
||||
h1 {margin-top: 50px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { padding: 5px 5px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.detail_table td.label { min-width: 100px; width: 8%;}
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="catalog_wrapper">
|
||||
<div id="catalog">
|
||||
<ul>
|
||||
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
|
||||
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
|
||||
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
|
||||
<ul>
|
||||
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
|
||||
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
<div id="content">
|
||||
<h1><a name="about">Synthesis Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>GowinSynthesis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\Users\koray\Documents\gowin\ALU\src\addition.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\ALU.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\arithmeticUnit.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\BinaryToBCD.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\dabble.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\fulladder.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\fullsubtraction.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\halfadder.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\halfsubtraction.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\logicUnit.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\multiplier.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\opCode.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\selector.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\subtraction.v<br>
|
||||
C:\Users\koray\Documents\gowin\ALU\src\top.v<br>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">GowinSynthesis Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.10.03 (64-bit)</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Thu Jan 23 05:43:09 2025
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="summary">Synthesis Details</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Top Level Module</td>
|
||||
<td>top</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Synthesis Process</td>
|
||||
<td>Running parser:<br/> CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.085s, Peak memory usage = 402.914MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 402.914MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 402.914MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 402.914MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 402.914MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 402.914MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 402.914MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 402.914MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 402.914MB<br/>Generate output files:<br/> CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 402.914MB<br/></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Total Time and Memory Usage</td>
|
||||
<td>CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 402.914MB</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="resource">Resource</a></h1>
|
||||
<h2><a name="usage">Resource Usage Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Port </b></td>
|
||||
<td>28</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Buf </b></td>
|
||||
<td>28</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    IBUF</td>
|
||||
<td>14</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    OBUF</td>
|
||||
<td>14</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>LUT </b></td>
|
||||
<td>141</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT2</td>
|
||||
<td>16</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT3</td>
|
||||
<td>36</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT4</td>
|
||||
<td>89</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="utilization">Resource Utilization Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
<td><b>Utilization</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Logic</td>
|
||||
<td>141(141 LUT, 0 ALU) / 20736</td>
|
||||
<td><1%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Register</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as Latch</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as FF</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">BSRAM</td>
|
||||
<td>0 / 46</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
56
gowin/ALU/impl/gwsynthesis/ALU_syn_resource.html
Normal file
56
gowin/ALU/impl/gwsynthesis/ALU_syn_resource.html
Normal file
@ -0,0 +1,56 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Hierarchy Module Resource</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
h1 {text-align: center; }
|
||||
h1 {margin-top: 36px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { align = "center"; padding: 5px 2px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="content">
|
||||
<h1>Hierarchy Module Resource</h1>
|
||||
<table>
|
||||
<tr>
|
||||
<th class="label">MODULE NAME</th>
|
||||
<th class="label">REG NUMBER</th>
|
||||
<th class="label">ALU NUMBER</th>
|
||||
<th class="label">LUT NUMBER</th>
|
||||
<th class="label">DSP NUMBER</th>
|
||||
<th class="label">BSRAM NUMBER</th>
|
||||
<th class="label">SSRAM NUMBER</th>
|
||||
<th class="label">ROM16 NUMBER</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">top (C:/Users/koray/Documents/gowin/ALU/src/top.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">13</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
<td class="label">    |--s1
|
||||
(C:/Users/koray/Documents/gowin/ALU/src/top.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">128</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
4
gowin/ALU/impl/gwsynthesis/ALU_syn_rsc.xml
Normal file
4
gowin/ALU/impl/gwsynthesis/ALU_syn_rsc.xml
Normal file
@ -0,0 +1,4 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Module name="top" Lut="13" T_Lut="141(13)">
|
||||
<SubModule name="s1" Lut="128" T_Lut="128(128)"/>
|
||||
</Module>
|
||||
Reference in New Issue
Block a user