kaltinsoy/4-bit-ALU
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k0rrluna
2025-01-23 07:22:58 +03:00
parent 6080927957
commit 2cf2de94d9
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@ -1,3 +1 @@
*.v linguist-language=Verilog *.v linguist-language=Verilog
*.sv linguist-language=SystemVerilog