38 lines
982 B
Verilog
38 lines
982 B
Verilog
module logicUnitTB ();
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reg [2:0] opCode;
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reg [3:0] A, B;
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wire [3:0] resultA, resultO, resultX;
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logicUnit uut (
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.opCode(opCode),
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.A(A),
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.B(B),
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.resultA(resultA),
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.resultO(resultO),
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.resultX(resultX)
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);
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initial begin
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$dumpfile("logicUnit.vcd");
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$dumpvars;
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opCode = 3'b001; A = 4'b0001; B = 4'b0001; #2;
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opCode = 3'b001; A = 4'b0011; B = 4'b0001; #2;
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opCode = 3'b001; A = 4'b1001; B = 4'b1001; #2;
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opCode = 3'b001; A = 4'b1111; B = 4'b1111; #2;
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opCode = 3'b001; A = 4'b0000; B = 4'b0000; #2;
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opCode = 3'b010; A = 4'b0001; B = 4'b0101; #2;
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opCode = 3'b010; A = 4'b1001; B = 4'b0101; #2;
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opCode = 3'b010; A = 4'b0001; B = 4'b1111; #2;
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opCode = 3'b010; A = 4'b0000; B = 4'b0101; #2;
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opCode = 3'b100; A = 4'b0000; B = 4'b0101; #2;
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opCode = 3'b100; A = 4'b0000; B = 4'b0000; #2;
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opCode = 3'b100; A = 4'b0000; B = 4'b0101; #2;
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opCode = 3'b100; A = 4'b1111; B = 4'b1111; #2;
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$finish;
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end
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endmodule
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